This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-controlled delay line. By using multi-band technology the proposed DLL can provide wider range and lower jitter compared to those of other methods. Frequency can be ranged from 250MHz to 900MHz is using TSMC 0.18um process with 1.8V supply voltage. The other implement is using UMC 90nm 1P9M CMOS process with 1V supply voltage. The frequency can be ranged from 33MHz to 300MHz.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0716108-103017 |
| Date | 16 July 2008 |
| Creators | Hsu, Yi-hsi |
| Contributors | Chia-Hsiung Kao, Ko-Chi Kuo, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0716108-103017 |
| Rights | not_available, Copyright information available at source archive |
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