A voltage controlled oscillator (VCO), that generates a periodic signal whose frequency is tuned by a voltage, is a key building block in any integrated circuit systems. A sine wave oscillator can be used for a built-in self testing where high linearity is required. A bandpass filter (BPF) based oscillator is a preferred solution, and high quality factor (Q-factor) is needed to improve the linearity. However, a stringent linearity specification may require very high Q-factor, not practical to implement. To address this problem, a frequency harmonic shaping technique is proposed. It utilizes a finite impulse response filter improving the linearity by rejecting certain harmonics. A prototype SC BPF oscillator with an oscillating frequency of 10 MHz is designed and measurement results show that linearity is improved by 20 dB over a conventional oscillator. In radio frequency area, preferred oscillator structures are an LC oscillator and a ring oscillator. An LC oscillator exhibits good phase noise but an expensive cost of an inductor is disadvantageous. A ring oscillator can be built in standard CMOS process, but suffers due to a poor phase noise and is sensitive to supply noise. A RC BPF oscillator is proposed to compromise the above difficulties. A RC BPF oscillator at 2.5 GHz is designed and measured performance is better than ring oscillators when compared using a figure of merit. In particular, the frequency tuning range of the proposed oscillator is superior to the ring oscillator. VCO is normally incorporated with a frequency synthesizer (FS) for an accurate frequency control. In an integer-N FS, reference spur is one of the design concerns in communication systems since it degrades a signal to noise ratio. Reference spurs can be rejected more by either the lower loop bandwidth or the higher loop filter. But the former increases a settling time and the latter decreases phase margin. An adaptive lowpass filtering technique is proposed. The loop filter order is adaptively increased after the loop is locked. A 5.8 GHz integer-N FS is designed and measurement results show that reference spur rejection is improved by 20 dB over a conventional FS without degrading the settling time. A new pulse interleaving technique is proposed and several design modifications are suggested as a future work.

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A Rail to Rail Differential Control Delay Line using multi-band technology can provide wider range on a delay-locked loop (DLL) is proposed in this thesis. Delay-Locked Loops (DLLs) have been widely used for clock deskew instead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. The main object of this thesis is the description and discussion in Delay-Locked Loop and Rail to Rail Differential Control Delay Line; uses TSMC 0.18£gm 1P6M CMOS process to design a 70 MHz¡ã750 MHz DLL and the supply voltage is 1.8V. This thesis is characterized by utilizing rail to rail input to reduce noise interference and enhance the signal integrity¡]low distortion, low noise, low power and high gain¡^.By the phase selection circuit is used to extend operation frequency. The operate frequency range of DLL is 70MHz to 750MHz, the power consumption of the Entire system is less than 32mW. The phase error is 10 ps at 70MHz and <10 ps at 750MHz in lock. The proposed DLL can provide wider range and lower jitter in this thesis.

This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-controlled delay line. By using multi-band technology the proposed DLL can provide wider range and lower jitter compared to those of other methods. Frequency can be ranged from 250MHz to 900MHz is using TSMC 0.18um process with 1.8V supply voltage. The other implement is using UMC 90nm 1P9M CMOS process with 1V supply voltage. The frequency can be ranged from 33MHz to 300MHz.

The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage, the design also possesses another feature, i.e., fast locked time. The second topic is the half-swing PLA circuit. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced. The third topic is a novel design of a the 1.0 GHz pipelining 8-bit CLA based on the architecture we mentioned in the second topic. The operating clock frequency is 1.0 GHz and the output of the addition of two 8-bit binary numbers is done in 2 cycles ( 2.0 ns ).

As an increasing number of distributed power generation systems (DPGS) are being connected to the utility grid, there is a growing requirement for the DPGS to be able to ride through short grid disturbances. This requires improvements to be made to the grid-side control scheme of the DPGS. An important part of the grid-side control scheme is the grid synchronization method, which is responsible for tracking the phase angle of the grid voltage vector. The state-of-the-art grid synchronization methods being used today are phase-locked loops. This thesis presents a modified phase-locked loop which is more robust towards grid disturbances. It consists of a multi-block adaptive notch filter (ANF) integrated into a conventional three-phase synchronous reference frame phase-locked loop (SRF-PLL). The addition of the multi-block ANF to the system allows it to become frequency adaptive. Also, since the multi-block ANF consists of multiple ANF blocks in parallel with one another, the system is able to remove multiple input signal distortions. Thus, the proposed system is able to eliminate the double frequency ripple that is caused in the conventional three-phase SRF-PLL by input unbalance, as well as harmonic errors, despite the presence of frequency variations in the input signal. Simulation results found using Matlab/Simulink, and experimental results found using the dSPACE DS1103 DSP board, demonstrate the feasibility of the modified SRF-PLL. Also, the modified SRF-PLL is compared to a conventional three-phase SRF-PLL, as well as to a conventional three-phase SRF-PLL with a simple notch filter, and the advantages of the modified SRF-PLL are discussed. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-12-17 12:38:02.589

A successive approximation register (SAR) circuit is adopted to control the digital delay line in the delay-locked loop (DLL) to achieve very fast locking effect in this proposed thesis. And in order to get low power consumption results, a loop state controller (LSC) is utilized to disable most of circuit. Because it is more easily to design and the advantages of high stability of delay-locked loop (DLL) compared to phase-locked loop (PLL), delay-locked loop (DLL) is more widely used in the adjustment of the clock error in the high frequency situation. This proposed delay locked loop (DLL) is added a register and a multiplexer in the feedback path. And the multiplexer does select which n-bit digital control code shall be read into the delay line; as the loop is locked, the path goes through the register is chosen to enter the sleep state ,and disable part of the circuit to make it into power saving mode. When entering the sleep state, the register provides the fixed input code; the phase error comparator (PEC) will keep tracking whether the frequency changes due to process, voltage, temperature and load (PVTL) variation uninterruptedly. Once there is something changed, the PEC will send a signal to inform the loop state controller (LSC) to enable the circuit from the sleep state, when the clock has to be locked again. And it just has 6 cycles time to relock, the lock range is form 150MHz to 900MHz. The power consuming are 15mW in lock mode and 9mW in sleep mode.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / FLL’s are extensively used for fast carrier synchronization. A common approach to meet the wide acquisition range and sufficiently small tracking error requirements is to adopt the wide or narrow band FLL loop in the acquisition and tracking modes and direct switching the loop. The paper analyze the influence of direct switching on performance, including the narrow band loop convergence, transition time etc. and propose applying the Kalman filtering theory to realize the seamless switching (SS) with time-varying loop gains between the two different loop tracking state. The SS control gains for the high dynamic digital spread spectrum receiver is derived. Simulation results for the SS compared to the direct switching demonstrate the improved performance.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / Presentation for ITC 98 of Alcatel Espace last studies and developments regarding TTC Products This document lays on 3 parts: · a technical point of view · a technology/design description · a synthesis showing main performance and results

Made available in DSpace on 2014-06-12T17:37:50Z (GMT). No. of bitstreams: 2 arquivo5359_1.pdf: 2762932 bytes, checksum: 0ca3cda75d19c5289f1914aaa550bbc1 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2008 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O uso de conversores de freqüência CC/CA para integrar a energia renovável como uma fonte de geração distribuída tem se tornado cada vez mais comum. Em tais aplicações, a sincronização com o vetor tensão da rede é fundamental para o controle do conversor, particularmente considerando os novos requisitos de suportabilidade a afundamentos de tensão demandados das gerações distribuídas atualmente. Este trabalho propõe um novo método de sincronização aplicado ao controle de conversores de freqüência apresentado-se imune a condições anormais de operação da rede. Quatro outros métodos de sincronização encontrados na literatura são apresentados enfatizando-se suas capacidades de fornecerem respostas corretas diante de tensões desequilibradas e distorcidas. O método proposto é simulado computacionalmente e comparado às demais técnicas. Os resultados experimentais também são mostrados, com o qual o novo método consegue eliminar a influência de desequilíbrios e harmônicos na estimação da fase, da freqüência e da magnitude do vetor tensão da rede. O método proposto é modelado como aplicado ao controle do conversor de uma turbina eólica conectada ao sistema elétrico. São implementadas duas estratégias de controle do conversor do lado da rede para avaliar a independência dos resultados em relação a técnica de controle de corrente. Afundamentos momentâneos de tensão no ponto de conexão são simulados e os resultados obtidos com o método proposto mostraram que a turbina eólica não perdeu a estabilidade