Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable effective-numberof-bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two different test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two different ways, but both of them utilized the low jitter design technique. In first test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

A Rail to Rail Differential Control Delay Line using multi-band technology can provide wider range on a delay-locked loop (DLL) is proposed in this thesis. Delay-Locked Loops (DLLs) have been widely used for clock deskew instead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. The main object of this thesis is the description and discussion in Delay-Locked Loop and Rail to Rail Differential Control Delay Line; uses TSMC 0.18£gm 1P6M CMOS process to design a 70 MHz¡ã750 MHz DLL and the supply voltage is 1.8V. This thesis is characterized by utilizing rail to rail input to reduce noise interference and enhance the signal integrity¡]low distortion, low noise, low power and high gain¡^.By the phase selection circuit is used to extend operation frequency. The operate frequency range of DLL is 70MHz to 750MHz, the power consumption of the Entire system is less than 32mW. The phase error is 10 ps at 70MHz and <10 ps at 750MHz in lock. The proposed DLL can provide wider range and lower jitter in this thesis.

This thesis presents a delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-controlled delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-controlled delay line. By using multi-band technology the proposed DLL can provide wider range and lower jitter compared to those of other methods. Frequency can be ranged from 250MHz to 900MHz is using TSMC 0.18um process with 1.8V supply voltage. The other implement is using UMC 90nm 1P9M CMOS process with 1V supply voltage. The frequency can be ranged from 33MHz to 300MHz.

As memory I/O bandwidth continues to increase beyond the current multi-gigabit rates for high performance computer systems, there remains a need for a stable and robust method of clock synchronization capable of transferring data reliability between main memory and a CPU memory controller. A Delay Locked Loop (DLL) is often utilized in such a system where synchronization and removal of clock skew are necessary. Synchronization in DLL’s is carried out by continually adjusting the phase of a clock signal by adding or removing delay based on feedback provided by a Phase Detector (PD). Once phase alignment occurs, the DLL is said to be in a “Locked” state. Delay can be produced with either a VCDL (Voltage Controlled Delay Line), or a DCDL (Digitally Controlled Delay Line). Each type of delay line has their own benefits and drawbacks, many of which will be discussed throughout this paper. This thesis provides an overview of previous DLL design research, and presents a functional 45nm CMOS, 200-833 MHz delay locked loop.

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-de ned radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, o set mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable e ective-numberof- bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two di erent test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two di erent ways, but both of them utilized the low jitter design technique. In rst test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

A successive approximation register (SAR) circuit is adopted to control the digital delay line in the delay-locked loop (DLL) to achieve very fast locking effect in this proposed thesis. And in order to get low power consumption results, a loop state controller (LSC) is utilized to disable most of circuit. Because it is more easily to design and the advantages of high stability of delay-locked loop (DLL) compared to phase-locked loop (PLL), delay-locked loop (DLL) is more widely used in the adjustment of the clock error in the high frequency situation. This proposed delay locked loop (DLL) is added a register and a multiplexer in the feedback path. And the multiplexer does select which n-bit digital control code shall be read into the delay line; as the loop is locked, the path goes through the register is chosen to enter the sleep state ,and disable part of the circuit to make it into power saving mode. When entering the sleep state, the register provides the fixed input code; the phase error comparator (PEC) will keep tracking whether the frequency changes due to process, voltage, temperature and load (PVTL) variation uninterruptedly. Once there is something changed, the PEC will send a signal to inform the loop state controller (LSC) to enable the circuit from the sleep state, when the clock has to be locked again. And it just has 6 cycles time to relock, the lock range is form 150MHz to 900MHz. The power consuming are 15mW in lock mode and 9mW in sleep mode.

Ultra-Wideband ¡}UWB¡~Communication Technology is one of the potential technologies in indoor wireless communication applications. Because of the property of fine resolution of transmitted signal by UWB, it is powerful on indoor location applications. In the first place, we need to estimate the time of arrival based on the wireless location applications. Whether synchronization between the template signals and received signals affects directly the SNR of the estimator output and decreases the ranging accuracy. Because of the transmitted signal is the type of impulse radio for UWB system, it is more important on the time accuracy of the internal oscillator. In the thesis, we utilize the Delay-Locked Loop ¡}DLL¡~ structure with Self-tuning function to reduce the timing jitter in the internal oscillator. We can improve the stability in the tracking loop and utilize multipath canceller to cancel the multipath interference in the indoor environment. When reaching synchronization between the template signal and received signal by using the tracking loop, we can improve ranging accuracy and increase location precision according to the received signal.

Time-to-digital converters (TDC) are widely used in light-detection-and-ranging (LIDAR) systems to measure the time-of-flight. Conventional TDCs are sensitivity to process, voltage, and temperature (PVT) variations. Recent work utilizing the stochastic delay-line TDC architecture has demonstrated excellent robustness against PVT variations. But important issues affecting the linearity of a stochastic delay-line TDC has yet to be recognized and addressed.This thesis rigorously analyzes the problem of linearity of a stochastic delay-line TDC and formulates an intuitive theory to predict the linearity performance. Apolarvisualization of the phase distribution of a delay line is proposed to aid the analysis. Based on the results of this study, this thesis proposes a stochastic delay-line TDC employing a delay-locked loop (DLL) to guarantee linearity over PVT variations and to reduce the number of redundant bits. The proposed TDC is implemented in a 0.18 µm CMOS process to validate the linearity theory and the proposed solution. The 8-bit TDC samples at 60 MHz and demonstrates a linear-number-of-bit of 6.36 with only 2-bit redundancy. Consuming 25 mW from a 1.8 V supply, the TDC yields a figure-of-merit of 5.04 pJ/conversion-step. With the DLL turned off, the integral nonlinearity (INL) degrades by about a factor of two, verifying the effectiveness of the proposed solution. The TDC is measured at different temperatures and supply voltages to demonstrate robustness against PVT variations. The measurement results show excellent agreement with the behavioral simulations.

A Delay-Locked Loop (DLL) for the generation of multiple clock phases/delays is proposed. Several new techniques are used to help enhance the DLLs performance, specifically, to achieve wide lock range, short locking time, and reduced jitter. The DLL can be used for a variety of applications which require precise time intervals or phase shifts. The phase detector (PD), charge pump (CP), and voltage-controlled delay line (VCDL) are the three most important blocks in a DLL. In our research, we have proposed a novel structure which integrates the functionality of both the PD and CP. By using this structure, a fast switching speed can be achieved. Moreover, the combined PD and CP also lead to reduced chip area and better jitter performance. A novel phase detection algorithm is developed and implemented in the combined PD and CP structure. This algorithm also involves a start-control circuit to avoid locking failure or false lock to harmonics. With the help of this algorithm, the proposed DLL is able to achieve lock as long as the minimum VCDL delay is less than one reference clock cycle, which is the largest possible lock range that can be achieved by the DLL. The VCDL uses fully differential signaling to minimize jitter. The delay stage of the VCDL is built with a differential topology using symmetrical loads and replica-feedback biasing, which provides a low sensitivity to supply and substrate noise as well as a wide tuning range. In addition, a shift-averaging technique is used to improve the matching between delay stages and thus to equalize the delay of each individual stage.

Abstract This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Yet, the time interval measurement system must provide an immediate and unambiguous measurement result over the full dynamic range. It must be made sure that the readings from the counter and the interpolators are always consistent with very high probability. Therefore, the operation of the counter is controlled with a synchronising logic that is in turn controlled with the interpolation result. Another synchronising logic makes it possible to synchronise the timing signals with multiphase time-interleaved clock signals as if the synchronising was done with a GHz-level clock, and enables multi-stage interpolation. Multi-stage interpolation reduces the number of delay cells and registers needed. The delay line interpolators are stabilised with nested delay-locked loops, which leads to good stability and makes it possible to improve single-shot precision with a single look-up table containing the integral nonlinearities of the interpolators measured at the room temperature. A multi-channel prototype TDC was fabricated in a 0.6 μm digital CMOS process. The prototype reaches state-of-the-art rms single-shot precision of better than 20 ps and low power consumption of 50 mW as an integrated TDC.