Studies on Synthesis Methods for Efficient Optical Logic Circuits / 高性能な光論理回路の合成手法に関する研究

Description

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24748号 / 情博第836号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 湊 真一, 教授 橋本 昌宜, 教授 岡部 寿男 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

Links & Downloads

1. http://hdl.handle.net/2433/283867
2. 10.14989/doctor.k24748
3. 14301

Tags

Photonic integrated circuit

Logic synthesis

Binary decision diagram

Nanophotonic device

Design automation

007

Additional Fields

Identifer	oai:union.ndltd.org:kyoto-u.ac.jp/oai:repository.kulib.kyoto-u.ac.jp:2433/283867
Date	23 March 2023
Creators	Matsuo, Ryosuke
Contributors	松尾, 亮祐, マツオ, リョウスケ
Publisher	Kyoto University, 京都大学
Source Sets	Kyoto University
Language	English
Detected Language	English
Type	doctoral thesis, Thesis or Dissertation
Rights	Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits"", doi:10.1587/transfun.E102.A.1751, Copyright(C)2019 IEICE. ""A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits"", doi:10.1587/transfun.2020KEP0018, Copyright(C)2021 IEICE. ""BDD-based Synthesis of Optical Logic Circuits Exploiting Wavelength Division Multiplexing"", doi:10.1145/3287624.3287703. ""A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing"", doi:10.1109/ISVLSI49217.2020.000-9, © 2020 IEEE. ""BDD Variable Ordering for Minimizing Power Consumption of Optical Logic Circuits"", doi:10.1109/ISVLSI51109.2021.00028, © 2021 IEEE. ""Space and Power Reduction in BDD-based Optical Logic Circuits Exploiting Dual Ports"", doi:10.23919/DATE54114.2022.9774637.