Phase locked loops (PLL) are used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator, and de-modulator. In many circuits, PLL must provide an output clock to follow the input clock closely. For high speed environments, the noises also rise up. Noises mainly come from the power supply and substrate. They produce jitter. A low jitter design is important in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator (VCO) which has the largest jitter in PLL system.
We propose a low jitter voltage controlled oscillator designed in TSMC 0.35£gm 2P4M Mixed-Signal process technology. We include a regulator to reduce jitter by increasing the VCO PSRR. This structure also provides a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0715104-141351 |
| Date | 15 July 2004 |
| Creators | Tzuhsuan, Peng |
| Contributors | Shyh-Jye Jou, Yao-Tsung Tsai, Chia-Hsiung Kao, Jyi-Tsong Lin |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715104-141351 |
| Rights | unrestricted, Copyright information available at source archive |
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