Phase locked loops (PLL) are used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator, and de-modulator. In many circuits, PLL must provide an output clock to follow the input clock closely. For high speed environments, the noises also rise up. Noises mainly come from the power supply and substrate. They produce jitter. A low jitter design is important in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator (VCO) which has the largest jitter in PLL system. We propose a low jitter voltage controlled oscillator designed in TSMC 0.35£gm 2P4M Mixed-Signal process technology. We include a regulator to reduce jitter by increasing the VCO PSRR. This structure also provides a high linearity gain (Kvco) which decreases the VCO jitter in the PLL circuit and improve the system stability.

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 µm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application. The proposed high-linearity up-conversion mixer with 1.01 mm ¡Ñ 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage. On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm ¡Ñ 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.

This thesis has described a wide tuning range transconductor combining source degeneration, cross-coupled, translinear loop to achieve high linearity. The transconductance tuning range from 220£gs to 1050£gs with 1V input range and the total harmonic distortion is -50dB with 0.6Vpp input voltage. And its application to a fifth-order elliptic low-pass Gm-C filter for the front-end RF circuit is presented. In order to transform the passive element circuit into a Gm-C based filter, a GIC flow method has been used. The proposal Gm-C based filter achieve a with performance a low frequency filtering range from 5Mhz to 10Mhz by transconductance tuning.

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 £gm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application. The proposed high-linearity up-conversion mixer with 1.01 mm ¡Ñ 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage. On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm ¡Ñ 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.

People for long term exposed to an air-conditioned but highly humid environment are vulnerable to hyper-sensitivity or asthma triggered by fungi or dust mites. This thesis aims to develop a high-linearity and low-hysteresis capacitive relative humidity (RH) microsensor to more precisely accommodate the humidity of living spaces. To reduce the hysteresis and enhance the linearity, this research uses not only one polyimide (PI) thin film as a humidity sensing layer but also utilizes another PI thin film as a protecting layer of the top electrodes. To improve further the RH sensitivity and responding speed, interlacing out-of-plane electrodes are designed in the RH microsensor. The main processing steps of the RH sensor developed in this study involve at least five photolithographic and four thin film deposition processes. The influences of sensing area, number of electrode pairs and testing temperature on the sensitivity and sensing linearity of humidity microsensors were investigated. Based on the measurement results, the sensitivity apparently increase as well as the sensing area (2 mm ¡Ñ 2 mm: 0.12 pF/%RH, 3 mm ¡Ñ 3 mm: 0.48 pF/%RH, 5 mm ¡Ñ 5 mm: 1.09 pF/%RH), and decrease with the number of electrode pairs (40 pairs: 0.51 pF/%RH, 20 pairs: 0.4 pF/%RH) and increase with the testing temperature. The thesis has demonstrated that the capacitance of the RH sensor vary from the relative humidity with a very linear relationship (linearity: 98.8%~99.99%) over the range of 30~70%RH. Finally, to increase effectively the surface area and to reduce further the hysteresis, three-dimensional (3D) moisture entrances and exits were designed and a very low hysteresis value (0.5%RH) can be achieved.

No description available.

No description available.

Les systèmes de communication mobiles permettent l’utilisation de l’information en environnements complexes grâce à des dispositifs portables qui ont comme principale restriction la durée de leurs batteries. Des nombreux efforts se sont focalisés sur la réduction de la consommation d’énergie des circuits électroniques de ces systèmes, une fois que le développent des technologies des batteries ne avance pas au rythme nécessaire. En outre, les systèmes RF sont généralement conçus pour fonctionner de manière fixe, spécifiés pour le pire cas du lien de communication. Toutefois, ce scénario peut se produire dans une petite partie du temps, entraînant ainsi en perte d’énergie dans le reste du temps. La recherche des circuits RF adaptatifs, pour adapter le niveau du signal d'entrée pour réduire la consommation d'énergie est donc d'un grand intérêt et de l'importance. Dans la chaîne de réception radiofréquence, l'amplificateur à faible bruit (LNA) se montre un composant essentiel, autant pour les performances de la chaîne que pour la consommation d'énergie. Au cours des dernières décennies, des techniques pour la conception de LNAs reconfigurables ont été proposées et mises en oeuvre. Cependant, la plupart d'entre elles s’applique seulement au contrôle du gain, sans exploiter Le réglage de la linéarité et du bruit envisageant l'économie d'énergie. De plus,ces circuits occupent une grande surface de silicium, ce qui entraîne un coût élevé, ou NE correspondent pas aux nouvelles technologies CMOS à faible coût. L'objectif de cette étude est de démontrer la faisabilité et les avantages de l'utilisation d'un LNA reconfigurable numériquement dans une chaîne de réception radiofréquence, du point de vue de la consommation d'énergie et de coût de fabrication. / Mobile communication systems allow exploring information in complex environments by means of portable devices, whose main restriction is battery life. Once battery development does not follow market expectations, several efforts have been made in order to reduce energy consumption of those systems. Furthermore, radio-frequency systems are generally designed to operate as fixed circuits, specified for RF link worst-case scenario. However, this scenario may occur in a small amount of time, leading to energy waste in the remaining periods. The research of adaptive radio-frequency circuits and systems, which can configure themselves in response to input signal level in order to reduce power consumption, is of interest and importance. In a RF receiver chain, Low Noise Amplifier (LNA) stand as critical elements, both on the chain performance or power consumption. In the past some techniques for reconfigurable LNA design were proposed and applied. Nevertheless, the majority of them are applied to gain control, ignoring the possibility of linearity and noise figure adjustment, in order to save power. In addition, those circuits consume great area, resulting in high production costs, or they do not scale well with CMOS. The goal of this work is demonstrate the feasibility and advantages in using a digitally controlled LNA in a receiver chain in order to save area and power. / Os sistemas de comunicação móveis permitem a exploração da informação em ambientes complexos através dos dispositivos portáteis que possuem como principal restrição a duração de suas baterias. Como o desenvolvimento da tecnologia de baterias não ocorre na velocidade esperada pelo mercado, muitos esforços se voltam à redução do consumo de energia dos circuitos eletrônicos destes sistemas. Além disso, os sistemas de radiofrequência são em geral projetados para funcionarem de forma fixa, especificados para o cenário de pior caso do link de comunicação. No entanto, este cenário pode ocorrer em uma pequena porção de tempo, resultando assim no restante do tempo em desperdício de energia. A investigação de sistemas e circuitos de radiofrequência adaptativos, que se ajustem ao nível de sinal de entrada a fim de reduzir o consumo de energia é assim de grande interesse e importância. Dentro de cadeia de recepção de radiofrequência, os Amplificadores de Baixo Ruído (LNA) se destacam como elementos críticos, tanto para o desempenho da cadeia como para o consumo de potência. No passado algumas técnicas para o projeto de LNA reconfiguráveis foram propostas e aplicadas. Contudo, a maioria delas só se aplica ao controle do ganho, deixando de explorar o ajuste da linearidade e da figura de ruído com fins de economia de energia. Além disso, estes circuitos ocupam grande área de silício, resultando em alto custo, ou então não se adaptam as novas tecnologias CMOS de baixo custo. O objetivo deste trabalho é demonstrar a viabilidade e as vantagens do uso de um LNA digitalmente configurável em uma cadeia de recepção de radiofrequência do ponto de vista de custo e consumo de potência.