The first topic of this thesis presents a novel VGA (variable gain amplifier) design which is applied in the AGC (automatic gain control) loop of digital video broadcasting - terrestrial (DVB-T) receivers. A total of three digital variable gain amplifiers (DVGA) are cascaded to provide a 70 dB dynamic range and 95 MHz operation frequency. The proposed digital VGA implemented by 0.35um 2P4M CMOS technology possesses 70 dB dynamic tuning range with a 0.3 dB gain error and 95 MHz bandwidth, and the power consumption is found to be 32.7 mW given a 3.3 V power supply. The second topic presents a design of a 60 ps peak-to-peak jitter, 80MHz, phase-locked loop (PLL) circuit for DVB-T receivers. The simulation results using the TSMC (Taiwan Semiconductor Manu-facturing Company) 0.35um 2P4M CMOS process show that the proposed PLL achieves as low as 60 ps peak-to-peak jitter when the output frequency is 80 MHz and the power consumption is merely 10.5 mW given a 3.3 V power supply.

This thesis presents a 2.4GHz image-reject downconverter fabricated in TSMC 0.25 1P5M CMOS process. The integrated active filter can not only filter out the image signal, but also reduce noise figure degraded by parasitic capacitance in the circuit. The differential LC oscillator fabricated in TSMC 0.35 1P4M CMOS process has properties of low phase noise and wide frequency turning range. Finally, a variable gain amplifier implemented in GCS GaAs HBT process was designed using signal summing architecture. The architecture is advantageous to reducing noise, distortion and increasing operating frequency. This thesis has studied what cause the difference between measurement and simulation for better performance in the future design.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / This paper presents a new variable beamwidth antenna designed for use in telemetry tracking systems when a high gain/low gain antenna configuration is required. This antenna can be commanded to continuously vary its beamwidth between a high gain/narrow beamwidth mode of operation and a low gain/ wide beamwidth mode of operation. A design goal of a 4:1 increase in beamwidth has been set and a 3.0:1 increase has been achieved without causing any significant degradation in the shape of the antenna patterns and without generating exceedingly high sidelobes in the low gain setting. The beamwidth variation occurs continuously without any loss of data, boresight shift or jitter such as experienced with the operation of conventional implementations of the high gain/low gain antenna technique.

In this thesis, three broadband low-noise mixing circuits which use CMOS 130 nm technology are presented. As one of the first few stages in a receiving front-end, stringent requirements are posted on mixer performance. The Gilbert cell mixers have presented excellent properties and achieved wide applications. However, the noise of a conventional active Gilbert cell mixer is high. This thesis demonstrates both passive and active mixing circuits with improved noise performance while maintaining the advantages of the Gilbert cell-based mixing core. Furthermore, wide bandwidth and variable gain are implemented, making the designed mixers multi-functional, yet with compact sizes and low power consumptions. The first circuit is a passive 2x subharmonic mixer that works from 4.5 GHz to 8.5 GHz. The subharmonic mixing core is a two-stage passive Gilbert cell driven by a quadrature LO signal. Together with a noise-cancelling transconductor and an inverter-based TIA, this subharmonic mixer possesses an excellent broadband conversion gain and a low noise figure. Measurement results show a high conversion gain of 16 dB and a low average DSB NF of 9 dB. The second design is a broadband low-noise variable gain mixer which operates between 1 and 6 GHz. The transconductor stage is implemented with noise cancellation and current bleeding techniques. Series inductive peaking is used to extend the bandwidth. Gain variation is achieved by a current-steering IF stage. Measurements show a wide gain control range of 13 dB and a low noise performance over the entire frequency and gain range. The lowest DSB NF is 3.8 dB and the highest DSB NF is 14.2 dB. The Third design is a broadband low-noise mixer with linear-in-dB gain control scheme. Using the same transconductance stage with the second circuit, this design also works from 1 to 6 GHz. A 10 dB linear-in-dB gain control range is achieved using an R-r load network with a linear-in-dB error less than $\pm$ 0.5 dB. Low noise performance is achieved. For different frequencies and conversion gains, the lowest DSB NF is 3.8 dB and the highest DSB NF is 12 dB. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-10-02 04:37:31.606

Abstract This thesis studies the level of performance achievable using today's standard IC processes in the integrated RF subcircuits of the modern GSM base station. The thesis concentrates on those circuit functions, i.e. I/Q modulators, variable gain amplifiers and frequency synthesizers, most relevant for integration in the base station environment as pinpointed by studying the receiver/transmitter architectures available today. Several RF integrated circuits have been designed, fabricated and their level of performance measured. All main circuits were fabricated in a standard double-metal double-poly 1.2 and 0.8 μm BiCMOS process. Key circuit structures and their measured properties are: 90° phase shifter with ±1° phase error with VCC = 4.5…5.5 V and T = -10…+85 °C, I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz (2.0 mm × 2.0 mm, 100 mA, 5.0 V) with LO suppression of 38 dBc and image rejection of 41 dBc, temperature compensated DC to 1.5 GHz variable gain amplifier (1.15 mm × 2.00 mm, 100 mA, 5.0 V) with a linear 50 dB gain adjustment range, maximum gain of 18.5 dB and gain variation of 1 dB up to 700 MHz over the whole operating conditions range of VCC = 4.5…5.5 V and T = -10…+85 °C, a complete bipolar semicustom synthesizer (90…122 mA, 5.0 V) and two complete full-custom BiCMOS synthesizer chips including all building blocks of a PLL-based synthesizer except for the voltage controlled oscillator and the loop filter. The synthesizers include circuit structures such as ∼2 GHz multi-modulus divider and low-noise programmable phase detector/charge pump (18.7 pA/√Hz at Iout = 500 μA) and have an exemplar phase noise performance of -110 dBc/Hz at 200 kHz offset. One of the main problems of the integer-N PLL based synthesizer when used in a multichannel telecommunications system is the level of spurious signals at the output, when the synthesizer is optimised for fast frequency switching. Therefore, a method using only two current pulses to make the frequency step response of the loop faster, thus allowing a narrower loop bandwidth to be used for additional spur suppression, is proposed. The operation of the proposed speed-up method is analysed mathematically and verified by measurements of an existing RF-IC synthesizer operating at 800 MHz. Measurements show that simple current pulses can be used to speed up the channel switching of a practical RF synthesizer having a frequency step time in the tens of μs range. In the example, a 7.65 MHz frequency step was made seven times faster using the proposed method.

No description available.

This thesis proposes a dB-linear programmable variable gain amplifier (VGA) and a voltage peak detector with digital calibration for FPW-based antibody sensing system. In the first topic, a dB-linear programmable variable gain amplifier is proposed. By using two source followers as the input terminals, input signals with very low DC offset could be received. The linear local-feedback transconductors are employed to be trans-condurctor-stage and load-stage. Besides, a reconfiguration method is used to reduce the layout area and improve the linearity of the gain to attain gain error less than 0.86 dB measured on silicon. In the second topic, a voltage peak detector with digital calibration is proposed. The voltage peak of the input sine-wave signal is sampled and held by using an integra-tor, a digital-to-analog converter, and a voltage comparator to generate a square-wave signal. Besides, the voltage error caused by the propagation delay could be calibrated by the proposed digital calibration method. The frequency of input signal is up to 20 MHz and the voltage error is justified to be less than 0.81 % by simulations.

This thesis consists of two parts. Part one includes the design procedure and implementation of the building blocks for an RF tuner module used in the Digital Video Broadcasting ¡V Terrestrial ¡]DVB-T¡^system. It contains the comparison of several RF tuner architectures, frequency planning, and link-budget analysis. Measurement results for the designed tuner operating in the frequency range from 50 to 860 MHz show that the maximum power gain ranges from 49 to 57.6 dB. The entire range for gain control is over 60 dB. In the maximum gain state, the noise figure ranges form 6.8 to 11.5 dB, the output third-order interception point¡]OIP3¡^ranges from 11.7 to 13.8 dBm, and the image rejection is over 50 dB. By applying the simplified single-carrier modulation signals, the tuner can pass the DVB-T system specifications with respect to the adjacent-channel and overlapping-channel protection ratios. In part two, an RFIC design for low-noise variable-gain amplifier that can be used in the RF front end of DVB-T system is presented. It operates from 100 to 900 MHz and dissipates 59.4 mW under a 3.3-V power supply. In the maximum gain state, measurement results for this RFIC show that the noise figure is less than 4 dB, the maximum gain is more than 14 dB, and the OIP3 is about 6.8dBm. The entire gain control range is over 40 dB.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.