The design and implementation of mm-wave switches, variable attenuators, and a passive imaging system in 65-nm CMOS are presented. The design and analysis of shunt switches is presented with a demonstration circuit showing record performance for a single-pole single-throw switch with 1.6dB loss and 30dB isolation at 94GHz. Single-pole double-throw (SPDT) switches are shown, with 4dB insertion loss in the W-band (75-110GHz), and the only reported SPDT switch operating in the D-band (110-170GHz). A novel technique for implementing digitally controlled variable attenuation is presented, resulting in variable attenuation between 4 and 30dB in the W-band. Finally, a W-band radiometer is described integrating a record-high gain CMOS LNA, SPDT switch, and peak detector. This is the highest-frequency imaging system in CMOS with this level of integration, offering a responsivity over 90kV/W, and a noise-equivalent power less than 0.2pW/√Hz.

The design and implementation of mm-wave switches, variable attenuators, and a passive imaging system in 65-nm CMOS are presented. The design and analysis of shunt switches is presented with a demonstration circuit showing record performance for a single-pole single-throw switch with 1.6dB loss and 30dB isolation at 94GHz. Single-pole double-throw (SPDT) switches are shown, with 4dB insertion loss in the W-band (75-110GHz), and the only reported SPDT switch operating in the D-band (110-170GHz). A novel technique for implementing digitally controlled variable attenuation is presented, resulting in variable attenuation between 4 and 30dB in the W-band. Finally, a W-band radiometer is described integrating a record-high gain CMOS LNA, SPDT switch, and peak detector. This is the highest-frequency imaging system in CMOS with this level of integration, offering a responsivity over 90kV/W, and a noise-equivalent power less than 0.2pW/√Hz.

This thesis proposes a dB-linear programmable variable gain amplifier (VGA) and a voltage peak detector with digital calibration for FPW-based antibody sensing system. In the first topic, a dB-linear programmable variable gain amplifier is proposed. By using two source followers as the input terminals, input signals with very low DC offset could be received. The linear local-feedback transconductors are employed to be trans-condurctor-stage and load-stage. Besides, a reconfiguration method is used to reduce the layout area and improve the linearity of the gain to attain gain error less than 0.86 dB measured on silicon. In the second topic, a voltage peak detector with digital calibration is proposed. The voltage peak of the input sine-wave signal is sampled and held by using an integra-tor, a digital-to-analog converter, and a voltage comparator to generate a square-wave signal. Besides, the voltage error caused by the propagation delay could be calibrated by the proposed digital calibration method. The frequency of input signal is up to 20 MHz and the voltage error is justified to be less than 0.81 % by simulations.

The main subject of this thesis is to design a voltage peak detector for FPW-based IgE measurement systems. Therefore, two different peak detectors are proposed. The first voltage peak detector basically samples the input signal twice (double sampling) to reduce the ripples appearing during the sample and hold modes. This voltage peak detector also resolves the detection error of conventional voltage peak detectors when they are used to detect the output signal of FPW-based biosensors.The fastest signal which this voltage peak detector can detect is 10 MHz. The second voltage peak detector is composed of a coupling capacitor, an unity gain buffer, an 8th order voltage control voltage source(VCVS) low pass filter, and a non-inverting amplifier. The major difference of this design from the previous one is to filter and amplify the input signal. The specification requirements of the operational transconductance amplifier in this voltage peak detector can be relaxed thereafter. The resolution and performance of the sensing system are also improved. By replacing the conventional power MOS by a non-inverting amplifier, the charging time is reduced and over charge hazard is avoided. Besides, the speed of the entire system is enhanced. The fastest signal which this voltage peak detector can detect is 50 MHz and the precision is 0.357 %.

Master's Thesis deals with the complete proposal of light adaptability A/D converter. In the second chapter there are describes types of sensors. Third one describes the most used methods of light adaptability. In the fourth chapter there is describe the adaptability A/D conversion. Chapter 5 describes the block diagram. In the sixth chapter there is the design of all blocks of A/D converter. Finally in the chapter 7 there are construction documents for realization.