One critical component of the communication receiver of front-end system is the low-noise amplifier (LNA). For good sensitivity and dynamic range, the LNA should provide a low noise figure and maximum attainable power gain. Another concern is the linearity of the LNA. Strong signals produce intermodulation products in a frequency band close to the operating frequency that might affect the performance of the receiver. In many cases, the intermodulation products can be reduced by increasing the current through the active device. Hence, a trade-off between power consumption and linearity must be considered when designing the LNA. The thesis includes the bias network design, stability analysis, matching network design and layout design of the LNA RF module with layout simulation. The simulation has been performed using Advanced Design System (ADS) simulation software. After implementation of LNA on a PCB, the LNA is measured with the help of the power supply unit and vector network analyzer. The proposed design aim is to provide a low noise figure (NF) and high gain while maintaining the low power consumption.

ABSTRACT In this thesis, we investigate the amplification characteristics of gain-flattened L-band (1570-1600 nm) erbium-doped fiber amplifier (EDFA) by employing the 1480 nm bi-directional pumping configuration. L-Band EDFAs are attractive because the use of L-band and C-band (1530-1560 nm) EDFAs in parallel greatly expands the amplification wavelength region. We adjusted the length of erbium-doped fiber (EDF) to achieve the flat amplification characteristics in the 1573-1600 nm wavelength region without using gain equalizers. The L-band EDFA exhibited a signal gain of 23 dB with good uniformity (less than 1 dB) and a noise figure of 6.9 dB for a 1580 nm signal of 16-channel WDM system. We also used the simulation tools to investigate the characteristics of L-band EDFA with the same configuration. The simulation results quite agree with the experimental data.

This thesis deals with two kinds of RF CMOS low noise amplifiers (LNA). The low power LNA and the image-reject LNA. The impact of gain, noise figure, and stability on RF CMOS image-reject LNA has been studied. Through this study, the fundamental properties of image-reject LNA can be understood by a simple but physical concept. A current-reuse RF CMOS source-degenerated cascode LNA is also presented, which adopts a combination of source-degenerated NMOS inverter and Cascode topology to improve gain and noise figure, the existent and well-studied technique from the design standpoint, makes optimization of the stage easy. A modification of the proposed architecture is also presented, which adopts internal filters to achieve the image rejection without additional image-reject filters that degrade both noise figure and power consumption. It will be a good candidate for low power implementation of CMOS RF-IC. Both circuits¡¦ parameters except noise figures are simulated using TSMC 0.25 um RF CMOS component models. The noise models considered here include induced gate noise, thermal noise and shot noise [5]. The current-reuse source-degenerated NMOS inverter LNA noise figure is 0.7 dB, forward gain is 16 dB, and IIP3 is -15 dBm. The low power image-reject LNA noise figure is 0.7 dB, forward gain is 16 dB, IIP3 is -16 dBm, and image rejection is 20 dB at 1.6 GHz. Both LNAs operate at 2.4 GHz and consume about 6 mA under a 2.5 V voltage supply.

Design of the next generation (4G) systems is one of the most active and important area of research and development in wireless communications. The 2G and 3G technologies will still co-exist with the 4G for a certain period of time. Other applications such as wireless LAN (Local Area Network) and RFID are also widely used. As a result, there emerges a trend towards integrating multiple wireless functionalities into a single mobile device. Low noise amplifier (LNA), the most critical component of the receiver front-end, determines the sensitivity and noise figure of the receiver and is indispensable for the complete system. To satisfy the need for higher performance and diversity of wireless communication systems, three LNAs with different structures and techniques are proposed in the thesis based on the 4G applications. The first LNA is designed and optimized specifically for LTE applications, which could be easily added to the existing system to support different standards. In this cascode LNA, the nonlinearity coming from the common source (CS) and common gate (CG) stages are analyzed in detail, and a novel linear structure is proposed to enhance the linearity in a relatively wide bandwidth. The LNA has a bandwidth of 900MHz with the linearity of greater than 7.5dBm at the central frequency of 1.2GHz. Testing results show that the proposed structure effectively increases and maintains linearity of the LNA in a wide bandwidth. However, a broadband LNA that covers multiple frequency ranges appears more attractive due to system simplicity and low cost. The second design, a wideband LNA, is proposed to cover multiple wireless standards, such as LTE, RFID, GSM, and CDMA. A novel input-matching network is proposed to relax the tradeoff among noise figure and bandwidth. A high gain (>10dB) in a wide frequency range (1-3GHz) and a minimum NF of 2.5dB are achieved. The LNA consumes only 7mW on a 1.2V supply. The first and second LNAs are designed mainly for the LTE standard because it is the most widely used standard in the 4G communication systems. However, WiMAX, another 4G standard, is also being widely used in many applications. The third design targets on covering both the LTE and the WiMAX. An improved noise cancelling technique with gain enhancing structure is proposed in this design and the bandwidth is enlarged to 8GHz. In this frequency range, a maximum power gain of 14.5dB and a NF of 2.6-4.3dB are achieved. The core area of this LNA is 0.46x0.67mm2 and it consumes 17mW from a 1.2V supply. The three designs in the thesis work are proposed for the multi-standard applications based on the realization of the 4G technologies. The performance tradeoff among noise, linearity, and broadband impedance matching are explored and three new techniques are proposed for the tradeoff relaxation. The measurement results indicate the techniques effectively extend the bandwidth and suppress the increase of the NF and nonlinearity at high frequencies. The three proposed structures can be easily applied to the wideband and multi-standard LNA design.

This dissertation explores high-speed silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) bipolar complementary metal oxide semiconductor (BiCMOS) circuits for next-generation ground- and space-based millimeter-wave (MMW >= 30 GHz) communication front-ends and X-band (8 to 12 GHz) radar (radio detection and ranging) modules. The requirements of next-generation transceivers, for both radar and communication applications, are low power, small size, light weight, low cost, high performance, and high reliability. For this purpose, the high-speed circuits that satisfy the demanding specifications of next-generation transceivers are implemented in SiGe HBT BiCMOS technology, and the device-circuit interactions of SiGe HBTs to transceiver building blocks for performance optimization and radiation tolerance are investigated. For X-band radar module components, the dissertation covers: (1) The design of an ultra-low-noise X-band SiGe HBT low-noise-amplifier (LNA). (2) The design of low-loss shunt and series/shunt X-band Si CMOS single-pole double-throw (SPDT) switches. (3) The design of a low-power X-band SiGe HBT LNA for near-space radar applications. For MMW communication front-end circuits, the dissertation covers: (4) The design of an inductorless SiGe HBT ring oscillator for MMW operation. (5) The study of emitter scaling and device biasing on MMW SiGe HBT voltage-controlled oscillator (VCO) performance. (6) The study of proton radiation on MMW SiGe HBT transceiver building blocks.

ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, California / Due to vehicle dynamics in mobile systems, GPS signal reception may be blocked by the body of the vehicle. This paper discusses various studies made on some vehicles such as the Space Shuttle, various aircraft, and analyzes the implementation of dual GPS antenna systems. Constructive and destructive interference characteristics of signal combining are considered. The author suggests an approach which uses a delay line on one of the antennas while analyzing the front end C/N0 needed for L1 GPS reception. An embedded Excel spreadsheet provides a front-end Noise Figure (NF) calculation tool based on user selected parameters.

Silicon CMOS Technology is now the preferred process for low power wireless communication devices, although currently much noisier and slower than comparable processes such as SiGe Bipolar and GaAs technologies. However, due to ever-reducing gate sizes and correspondingly higher speeds, higher Ft CMOS processes are increasingly competitive, especially in low power wireless systems such as Bluetooth, Wireless USB, Wimax, Zigbee and W-CDMA transceivers. With the current 32 nm gate sized devices, speeds of 100 GHz and beyond are well within the horizon for CMOS technology, but at a reduced operational voltage, even with thicker gate oxides as compensation. This thesis investigates newer techniques, both from a systems point of view and at a circuit level, to implement an efficient transceiver design that will produce a more sensitive receiver, overcoming the noise disadvantage of using CMOS Silicon. As a starting point, the overall components and available SoC were investigated, together with their architecture. Two novel techniques were developed during this investigation. The first was a high compression point LNA design giving a lower overall systems noise figure for the receiver. The second was an innovative means of matching circuits with low Q components, which enabled the use of smaller inductors and reduced the attenuation loss of the components, the resulting smaller circuit die size leading to smaller and lower cost commercial radio equipment. Both these techniques have had patents filed by the University. Finally, the overall design was laid out for fabrication, taking into account package constraints and bond-wire effects and other parasitic EMC effects.

In this thesis, design aspects of fully integrated multibandmultistandard front-end receivers are investigated based onthree fundamental aspects: noise, linearity and operatingfrequency. System level studies were carried out to investigatethe effects of different modulation techniques, duplexing andmultiple access methods on the noise, linearity and selectivityperformance of the circuit. Based on these studies and thelow-cost consideration, zero-IF, low-IF and wideband-IFreceiver architectures are promising architectures. These havea common circuit topology in a direct connection between theLNA and the mixer, which has been explored in this work toimprove the overall RF-to-IF linearity. One front-end circuitapproach is used to achieve a low-cost solution, leading to anew multiband multistandard front-end receiver architecture.This architecture needs a circuit whose performance isadaptable due to different requirements specified in differentstandards, works across several RF-bands and uses a minimumamount ofexternal components. Five new circuit topologies suitable for a front-endreceiver consisting of an LNA and mixer (low-noise converter orLNC) were developed. A dual-loop wide-band feedback techniquewas applied in all circuits investigated in this thesis. Threeof the circuits were implemented in 0.18 mm RF-CMOS and 25 GHzbipolar technologies. Measurement results of the circuitsconfirmed the correctness of the design approach. The circuits were measured in several RF-bands, i.e. in the900 MHz, 1.8 GHz and 2.4 GHz bands, with S11 ranging from–9.2 dB to–17 dB. The circuits have a typicalperformance of 18-20 dB RF-to-IF gain, 3.5-4 dB DSB NF and upto +4.5 dBm IIP3. In addition, the circuit performance can beadjusted by varying the circuit’s first-stage biascurrent. The circuits may work at frequencies higher than 3GHz, as only 1.5 dB of attenuation is found at 3 GHz and nopeaking is noticed. In the CMOS circuit, the extrapolated gainat 5 GHz is about 15 dB which is consistent with the simulationresult. The die-area of each of the circuits is less than 1mm2.

The design and implementation of mm-wave switches, variable attenuators, and a passive imaging system in 65-nm CMOS are presented. The design and analysis of shunt switches is presented with a demonstration circuit showing record performance for a single-pole single-throw switch with 1.6dB loss and 30dB isolation at 94GHz. Single-pole double-throw (SPDT) switches are shown, with 4dB insertion loss in the W-band (75-110GHz), and the only reported SPDT switch operating in the D-band (110-170GHz). A novel technique for implementing digitally controlled variable attenuation is presented, resulting in variable attenuation between 4 and 30dB in the W-band. Finally, a W-band radiometer is described integrating a record-high gain CMOS LNA, SPDT switch, and peak detector. This is the highest-frequency imaging system in CMOS with this level of integration, offering a responsivity over 90kV/W, and a noise-equivalent power less than 0.2pW/√Hz.

The design and implementation of mm-wave switches, variable attenuators, and a passive imaging system in 65-nm CMOS are presented. The design and analysis of shunt switches is presented with a demonstration circuit showing record performance for a single-pole single-throw switch with 1.6dB loss and 30dB isolation at 94GHz. Single-pole double-throw (SPDT) switches are shown, with 4dB insertion loss in the W-band (75-110GHz), and the only reported SPDT switch operating in the D-band (110-170GHz). A novel technique for implementing digitally controlled variable attenuation is presented, resulting in variable attenuation between 4 and 30dB in the W-band. Finally, a W-band radiometer is described integrating a record-high gain CMOS LNA, SPDT switch, and peak detector. This is the highest-frequency imaging system in CMOS with this level of integration, offering a responsivity over 90kV/W, and a noise-equivalent power less than 0.2pW/√Hz.