The first topic of this thesis presents a novel VGA (variable gain amplifier) design which is applied in the AGC (automatic gain control) loop of digital video broadcasting - terrestrial (DVB-T) receivers. A total of three digital variable gain amplifiers (DVGA) are cascaded to provide a 70 dB dynamic range and 95 MHz operation frequency. The proposed digital VGA implemented by 0.35um 2P4M CMOS technology possesses 70 dB dynamic tuning range with a 0.3 dB gain error and 95 MHz bandwidth, and the power consumption is found to be 32.7 mW given a 3.3 V power supply. The second topic presents a design of a 60 ps peak-to-peak jitter, 80MHz, phase-locked loop (PLL) circuit for DVB-T receivers. The simulation results using the TSMC (Taiwan Semiconductor Manu-facturing Company) 0.35um 2P4M CMOS process show that the proposed PLL achieves as low as 60 ps peak-to-peak jitter when the output frequency is 80 MHz and the power consumption is merely 10.5 mW given a 3.3 V power supply.

This thesis presents a 2.4GHz image-reject downconverter fabricated in TSMC 0.25 1P5M CMOS process. The integrated active filter can not only filter out the image signal, but also reduce noise figure degraded by parasitic capacitance in the circuit. The differential LC oscillator fabricated in TSMC 0.35 1P4M CMOS process has properties of low phase noise and wide frequency turning range. Finally, a variable gain amplifier implemented in GCS GaAs HBT process was designed using signal summing architecture. The architecture is advantageous to reducing noise, distortion and increasing operating frequency. This thesis has studied what cause the difference between measurement and simulation for better performance in the future design.

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This thesis proposes a dB-linear programmable variable gain amplifier (VGA) and a voltage peak detector with digital calibration for FPW-based antibody sensing system. In the first topic, a dB-linear programmable variable gain amplifier is proposed. By using two source followers as the input terminals, input signals with very low DC offset could be received. The linear local-feedback transconductors are employed to be trans-condurctor-stage and load-stage. Besides, a reconfiguration method is used to reduce the layout area and improve the linearity of the gain to attain gain error less than 0.86 dB measured on silicon. In the second topic, a voltage peak detector with digital calibration is proposed. The voltage peak of the input sine-wave signal is sampled and held by using an integra-tor, a digital-to-analog converter, and a voltage comparator to generate a square-wave signal. Besides, the voltage error caused by the propagation delay could be calibrated by the proposed digital calibration method. The frequency of input signal is up to 20 MHz and the voltage error is justified to be less than 0.81 % by simulations.

This thesis consists of two parts. Part one includes the design procedure and implementation of the building blocks for an RF tuner module used in the Digital Video Broadcasting ¡V Terrestrial ¡]DVB-T¡^system. It contains the comparison of several RF tuner architectures, frequency planning, and link-budget analysis. Measurement results for the designed tuner operating in the frequency range from 50 to 860 MHz show that the maximum power gain ranges from 49 to 57.6 dB. The entire range for gain control is over 60 dB. In the maximum gain state, the noise figure ranges form 6.8 to 11.5 dB, the output third-order interception point¡]OIP3¡^ranges from 11.7 to 13.8 dBm, and the image rejection is over 50 dB. By applying the simplified single-carrier modulation signals, the tuner can pass the DVB-T system specifications with respect to the adjacent-channel and overlapping-channel protection ratios. In part two, an RFIC design for low-noise variable-gain amplifier that can be used in the RF front end of DVB-T system is presented. It operates from 100 to 900 MHz and dissipates 59.4 mW under a 3.3-V power supply. In the maximum gain state, measurement results for this RFIC show that the noise figure is less than 4 dB, the maximum gain is more than 14 dB, and the OIP3 is about 6.8dBm. The entire gain control range is over 40 dB.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

In this thesis the design of a MMIC vector modulator operating in 9GHz-10GHz band is investigated and performed. Sub-sections of the vector modulator are 4-port (4.8dB) 1200 phase shift relative to the dedicated port power splitter, digitally controlled variable gain amplifier and the in phase power combiner. Alternative methods are searched in order to implement the structure properly in the given frequency band. The final design is appropriate for MMIC structure. 4-port (4.8dB) 1200 phase shift relative to the dedicated port power splitter is studied. The performance is simulated and optimized first on Microwave Office, then on Advanced Design System (ADS) tools. Various methods to design a digitally controlled variable gain amplifier are studied. The final topology is simulated and optimized on ADS tool. An in phase power combiner is designed. The performance of the combiner is simulated and optimized on ADS tool. Lumped element models are replaced with CASWELL H-40 models to achieve a MMIC structure and a layout is drawn. The finalized vector modulator is simulated and optimized on ADS tool. Key words: MMIC, Vector Modulator, Digitally Controlled Variable Gain Amplifier, Layout

Die vorliegende Arbeit ist der analytischen Untersuchung und Weiterentwicklung von Methoden und Schaltungen zur Einstellung der Signalphase und -amplitude gewidmet. Hierbei wird zum Ziel gesetzt, die Leistungsfähigkeit dieser Schaltungen als analoge Hochfrequenz-Baugruppen in Empfangs- und Sendeschaltkreisen mit einem vergleichbaren oder geringerem schaltungstechnischen Aufwand und Strombedarf zu verbessern und dies anhand von Implementierungsbeispielen zu bestätigen. Die Dämpfungsglied-Topologien , T, überbrücktes T und X werden modelliert und hinsichtlich der Phasenbeeinflussung analysiert, sodass eine Bewertung ihrer Eignung durchgeführt werden kann. Weiterhin wird ein innovativer Ansatz zur Linearisierung der Steuerkennlinie vorgestellt und mit Hilfe einer Beispielschaltung mit einem Phasenfehler von 3 ° und einem Steuerlinearitätsfehler von 0,35 dB innerhalb der 1 dB Grenzfrequenz und einem Steuerbereich von 20 dB nachgewiesen. Die Arbeit bietet darüber hinaus eine analytische Betrachtung zu aktiven steuerbaren Verstärkern, welche die besondere Eignung der Gilbert-Zelle aufzeigt und eine geeignete Ansteuerschaltung ableitet. Am Beispiel nach diesem Prinzip entworfener Schaltkreise werden Phasenfehler von nur 0,4 ° innerhalb eines besonders hohen Stellbereichs von 36 dB demonstriert, wodurch eine Vergrößerung des Stellbereichs um den Faktor 4 und eine Verbesserung des Phasenfehlers um den Faktor 2 im Vergleich zum Stand der Technik erreicht wurde. Es wird der Zirkulator-Phasenschieber maßgeblich durch eine neuartige geeignete Ansteuerung verbessert. Damit werden die sonst für die Amplitudenbeeinflussung im Wesentlichen verantwortlichen Varaktoren überflüssig, ohne dabei den schaltungstechnischen Aufwand zu erhöhen. Eine Messung der entsprechenden Schaltung bestätigt dies mit einem Amplitudenfehler von nur 0,9 dB für einen Phasenstellbereich von 360 °, was einer Verringerung des Fehlers um den Faktor 3 im Vergleich zu herkömmlichen Zirkulator-Phasenschiebern entspricht. Abschließend wird der Funktionsnachweis mehrerer entworfener Vektor-Modulatoren mit einer effektiven Genauigkeit von bis zu 6 bit in Einzelschaltungen, Hybridaufbauten und schließlich im Rahmen eines vollständig integrierten Empfängerschaltkreises erbracht. Dieser erzielt eine Verdopplung der Reichweite bei einer um nur 35% höheren Leistungsaufnahme gegenüber einem herkömmlichen Kommunikationsverfahren (SISO). / The present work is dedicated to the investigation and enhancement of amplitude and phase control methods and circuits. The aim is to enhance the performance of these circuits in modern radio frequency transceivers with a comparable or even lower effort and power consumption. A prove of concept will be delivered with implementation examples. By means of models of the passive attenuator topologies , T, bridged-T and X, a thorough analysis is performed in order to compare them regarding their impact on the signal phase. Additionally, a novel approach to increase the control linearity of the attenuators is proposed and verified by measurements, showing a phase error of 3 ° and a control linearity error of 0,35 dB at the 1 dB corner frequency, successfully. The work also presents an investigation on variable gain amplifiers and reveals the superior performance of the Gilbert cell with respect to low phase variations. A cascode biasing circuit that supports these properties is proposed. Measurements prove this concept with relative phase errors of 0,4 ° over a wide attenuation control range of 36 dB thus cutting the error by half in a four times wider control range. The circulator based phase shifting approach is chosen and improved significantly by means of tuning the transconductor instead of the varactors thus removing their impact on signal amplitude. The approach is supported by measurements yielding an amplitude error of only 0,9 dB within a phase control range of 360 ° which corresponds to an improvement by a factor of three compared to recent circulator phase shifters. Finally, the design of several vector modulator topologies is shown with hardware examples of single chips, hybrid printed circuit boards and highly integrated system level ICs demonstrating a full receiver. By using improved variable gain amplifiers, an effective vector modulator resolution of 6 bit without calibration is achieved. Furthermore, a multiple-input multiple-output system is demonstrated that doubles the coverage range of common SISO systems with only 35% of additional power consumption.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico. / The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.