This paper proposes a multitier multilevel TSV diagnosis scheme for 3D ICs to achieve interconnect reliability and yield with targets of interconnect faults under stuck-at and open fault models. This scheme takes advantage of previous work of IEEE 1500 compatible interconnect test and diagnosis methods, and further develop a TSV detection and diagnosis method for 3D circuits. An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for 3D systems-on-chip (SOC) designs with heterogeneous cores is proposed. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the both vertical and horizontal ring generation algorithm achieves the maximum detectability for any interconnect.

We hypothesized that marked reductions in secretion of luteinizing hormone (LH) during transitional and anovulatory periods can be accounted for by similar reductions in hypothalamic gonadotropin-releasing hormone (GnRH) secretion. Catheters were inserted surgically into the intercavernous sinus (ICS) of seven non-pregnant mares via the superficial facial vein during the ovulatory season (August 12-23), fall transition (November 15-30), the anovulatory season (January 19 - February 1) and spring transition (March 24 - May 12). Catheter placement was confirmed and standardized in each mare by lateral radiography. Ovarian status was monitored throughout the study by transrectal ultrasonography and serum concentrations of progesterone. During the breeding season, ICS blood samples were collected at 5-min intervals for 8 h when the dominant follicle reached approximately 35 mm and estrous behavior was observed. All mares ovulated within 5 d after sampling, except one mare who ovulated < 24 h before sampling. During the fall, mares were anovulatory (n = 5) or had a final ovulation within 5 d following intensive sampling (n = 2). Winter anovulation sampling was performed when all mares were anovulatory. During spring transition, each mare was sampled just before the second ovulation of the season. Similar to the ovulatory season, mares were sampled when the dominant, preovulatory follicle reached approximately 35 mm and estrous behavior was observed. Mean concentrations of LH were markedly higher (P < 0.01) during the breeding season than during all other seasons. Lower mean concentrations of LH in the fall transition, winter anovulation and spring transition sampling periods occurred coincident with a similar reduction (P < 0.01) in amplitude of LH pulses. Unexpectedly, neither the frequency (pulse/8 h) of LH pulses, frequency and amplitude of GnRH pulses, nor mean concentrations of GnRH differed among seasons. In addition, there were no differences observed due to season in mean concentrations of FSH or amplitude of FSH pulses. However, a small but significant (P < 0.05) reduction in the frequency of FSH pulses was observed during fall transition compared to all other seasons. In summary, contrary to accepted dogma, these results indicate that the photoperiodic initiation of seasonal anovulation in the mare is mediated at the level of the anterior pituitary, and appears to occur through a dampening of gonadotroph responsiveness to an unchanging pattern and magnitude of GnRH secretion.

In the process of continuous scaling improvement under a single system-on-chip which contains millions of logic gates, testability of the design becomes more and more important and thus multiple scan tree test architecture can effectively reduce test time and test data simultaneously. In the current two-dimensional structure of the system-level chip, the interconnect has become one of the main factors in delay and power consumption, and thus optimizing interconnect becomes a very important topic. Especially, three-dimensional ICs, stacked multiple chips vertically by through-silicon-via technique, can be effective in reducing the length of the interconnects, power consumption and offering features of heterogeneous IC integration. In this research study, we consider three-dimensional chips in both respects of wire length and the scan output limits, and propose the test synthesis algorithm of multiple scan trees to reduce test cost for three dimensional integrated circuits.

We hypothesized that marked reductions in secretion of luteinizing hormone (LH) during transitional and anovulatory periods can be accounted for by similar reductions in hypothalamic gonadotropin-releasing hormone (GnRH) secretion. Catheters were inserted surgically into the intercavernous sinus (ICS) of seven non-pregnant mares via the superficial facial vein during the ovulatory season (August 12-23), fall transition (November 15-30), the anovulatory season (January 19 - February 1) and spring transition (March 24 - May 12). Catheter placement was confirmed and standardized in each mare by lateral radiography. Ovarian status was monitored throughout the study by transrectal ultrasonography and serum concentrations of progesterone. During the breeding season, ICS blood samples were collected at 5-min intervals for 8 h when the dominant follicle reached approximately 35 mm and estrous behavior was observed. All mares ovulated within 5 d after sampling, except one mare who ovulated < 24 h before sampling. During the fall, mares were anovulatory (n = 5) or had a final ovulation within 5 d following intensive sampling (n = 2). Winter anovulation sampling was performed when all mares were anovulatory. During spring transition, each mare was sampled just before the second ovulation of the season. Similar to the ovulatory season, mares were sampled when the dominant, preovulatory follicle reached approximately 35 mm and estrous behavior was observed. Mean concentrations of LH were markedly higher (P < 0.01) during the breeding season than during all other seasons. Lower mean concentrations of LH in the fall transition, winter anovulation and spring transition sampling periods occurred coincident with a similar reduction (P < 0.01) in amplitude of LH pulses. Unexpectedly, neither the frequency (pulse/8 h) of LH pulses, frequency and amplitude of GnRH pulses, nor mean concentrations of GnRH differed among seasons. In addition, there were no differences observed due to season in mean concentrations of FSH or amplitude of FSH pulses. However, a small but significant (P < 0.05) reduction in the frequency of FSH pulses was observed during fall transition compared to all other seasons. In summary, contrary to accepted dogma, these results indicate that the photoperiodic initiation of seasonal anovulation in the mare is mediated at the level of the anterior pituitary, and appears to occur through a dampening of gonadotroph responsiveness to an unchanging pattern and magnitude of GnRH secretion.

abstract: Utilities infrastructure like the electric grid have been the target of more sophisticated cyberattacks designed to disrupt their operation and create social unrest and economical losses. Just in 2016, a cyberattack targeted the Ukrainian power grid and successfully caused a blackout that affected 225,000 customers. Industrial Control Systems (ICS) are a critical part of this infrastructure. Honeypots are one of the tools that help us capture attack data to better understand new and existing attack methods and strategies. Honeypots are computer systems purposefully left exposed to be broken into. They do not have any inherent value, instead, their value comes when attackers interact with them. However, state-of-the-art honeypots lack sophisticated service simulations required to obtain valuable data. Worst, they cannot adapt while ICS malware keeps evolving and attacks patterns are increasingly more sophisticated. This work presents HoneyPLC: A Next-Generation Honeypot for ICS. HoneyPLC is, the very first medium-interaction ICS honeypot, and includes advanced service simulation modeled after S7-300 and S7-1200 Siemens PLCs, which are widely used in real-life ICS infrastructures. Additionally, HoneyPLC provides much needed extensibility features to prepare for new attack tactics, e.g., exploiting a new vulnerability found in a new PLC model. HoneyPLC was deployed both in local and public environments, and tested against well-known reconnaissance tools used by attackers such as Nmap and Shodan's Honeyscore. Results show that HoneyPLC is in fact able to fool both tools with a high level of confidence. Also, HoneyPLC recorded high amounts of interesting ICS interactions from all around the globe, proving not only that attackers are in fact targeting ICS systems, but that HoneyPLC provides a higher level of interaction that effectively deceives them. / Dissertation/Thesis / Masters Thesis Computer Science 2020

As technology continues to scale to smaller geometries and newer dimensions (3-D), with increasingly complex manufacturing processes, the ability to reliably manufacture 100% defect-free circuitry becomes a significant challenge. While implementing additional circuitry to improve yield is economically justifiable, this thesis addresses the cost of defect tolerance by providing lower cost solutions or alternatively more defect tolerance for the same cost in state-of-the-art ICs, including three-dimensional ICs (3-D ICs). Conventional defect tolerance techniques involve incorporating redundancy into the design. This thesis introduces novel designs to maximize the utility of spare elements with minimal circuitry overhead, thereby improving the yield. One idea proposed is Selective Row Partitioning (SRP), a technique which allows a single spare column to be used to repair multiple defective cells in multiple columns. This is done by selectively decoding the row address bits when generating the select signals for the column multiplexers. This logically segments the spare column allowing it to replace different columns in different partitions of the row address space. All the chips are identical, but fuses are used to customize the row decoding circuitry on a chip-by-chip basis. An implementation procedure and results are presented which show improvement in overall yield at a minimal overhead cost. Moreover, new yield-enhancing design techniques for 3-D ICs are introduced. When assembling a 3-D IC, there are several degrees of freedom including which die are stacked together, in what order, and with what rotational symmetry. This thesis describes strategies for exploiting these degrees of freedom to reduce the cost and complexity of implementing defect tolerance. One strategy is to enable asymmetric repair capability within a 3-D memory stack by exploiting the degree of freedom that the order of the die in the stack can be selected. This technique optimizes the number of fuses, and in some cases, the number of spares as well, required to implement defect tolerance. Another innovative technique is to exploit rotational symmetry of the dies to do implicit reconfiguration to implement defect tolerance. Results show that leakage power and performance overhead for defect tolerance can be significantly reduced by this technique. / text

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

Next generation communication systems are reaching 110Gbps rates. At these frequencies, the skin effect and dielectric loss of copper cables cause inter-symbol interference (ISI) and frequency dependent loss, severely limiting the channel bandwidth. In this thesis, different methods for alleviating ISI are explored. The design of the critical blocks of an adaptive channel equalizer with up to two times oversampling are presented. The circuits were fabricated in a 0.13μm SiGe BiCMOS technology. The linear, adaptive equalizer operates up to 70Gbps and its measured S-parameters exhibit a single-ended peak gain of 12.2dB at 52GHz, allowing for 31dB of peaking between DC and 52GHz. Equalization is demonstrated experimentally at 59Gbps for a cable loss of 17.9dB. These results make it the fastest receive equalizer published to date. A retiming flip-flop operating between 72 and 118 GHz, the highest reported in silicon, is also designed and characterized, showing less than 500-fs jitter.

Industrial Control Systems (ICSs) are used to monitor and control critical infrastructure such as electricity and water. ICS were originally stand-alone systems, but are now widely being connected to corporate national IT networks, making remote monitoring and more timely control possible. While this connectivity has brought multiple benefits to ICS, such as cost reductions and an increase in redundancy and flexibility, ICS were not designed for open connectivity and therefore are more prone to security threats, creating a greater requirement for adequate security engineering approaches. The culture gap between developers and security experts is one of the main challenges of ICS security engineering. Control system developers play an important role in building secure systems; however, they lack security training and support throughout the development process. Security training, which is an essential activity in the defence-indepth strategy for ICS security, has been addressed, but has not been given sufficient attention in academia. Security support is a key means by which to tackle this challenge via assisting developers in ICS security by design. This thesis proposes a novel framework, the Industrial Control System Security Engineering Support (ICS-SES), which aims to help developers in designing secure control systems by enabling them to reuse secure design patterns and improve their security knowledge. ICS-SES adapts pattern-based approach to guide developers in security engineering, and an automated planning technique to provide adaptive on-the-job security training tailored to personal needs. The usability of ICS-SES has been evaluated using an empirical study in terms of its effectiveness in assisting the design of secure control systems and improving developers’ security knowledge. The results show that ICS-SES can efficiently help control system designers to mitigate security vulnerabilities and improve their security knowledge, reducing the difficulties associated with the security engineering process, and the results have been found to be statically significant. In summary, ICS-SES provides a unified method of supporting an ICS security by design approach. It fosters a development environment where engineers can improve their security knowledge while working in a control system production line.

This thesis is concerned with inter-vehicle communications supporting the deployment of future safety-related applications. Through use case analysis of the specific communica- tions requirements of safety related and traffic efficiency applications, a data dissemination framework is proposed that is able to meet the various message delivery requirements. More specifically, this thesis focuses on the subset of the proposed framework, which provides geocasting, i.e. addressing a geographical area on the road network, and local zone connectivity, providing neighbour awareness, for safety related applications. The enabling communications technology for inter-vehicle communications based on IEEE 802.11 wireless local area network devices and the associated lack of reliability it presents for the distribution of safety messages in broadcast mode, form the main topic of this thesis. A dissemination scheme for safety related inter-vehicular communication applica- tions, using realistic vehicular traffic patterns, is proposed, implemented and evaluated to demonstrate mechanisms for efficient, reliable and timely delivery of safety messages over an unreliable channel access scheme. The original contribution of this thesis is to propose a novel data dissemination protocol for vehicular environments, capable of simultaneously achieving significant economy of messaging, whilst maintaining near 100% reliable message delivery in a timely manner for a wide variety of highway traffic flow scenarios, ranging from sparsely, fragmented networks to dense, congested road networks. This is achieved through increased protocol complexity in inferring and tracking each vehicular node’s local environment, coupled with implementing adaptation to both local data traffic intensity and vehicular density. Adaptivity is achieved through creating and employing an empirical channel access delay model and embedding the stochastic delay distribution in decisions made at the network layer; this method of adaptivity is novel in itself. Moreover, unnecessary retransmissions arising from the inherent uncertainty of the wireless medium are suppressed through a novel three-step mechanism.