As technology continues to scale to smaller geometries and newer dimensions (3-D), with increasingly complex manufacturing processes, the ability to reliably manufacture 100% defect-free circuitry becomes a significant challenge. While implementing additional circuitry to improve yield is economically justifiable, this thesis addresses the cost of defect tolerance by providing lower cost solutions or alternatively more defect tolerance for the same cost in state-of-the-art ICs, including three-dimensional ICs (3-D ICs). Conventional defect tolerance techniques involve incorporating redundancy into the design. This thesis introduces novel designs to maximize the utility of spare elements with minimal circuitry overhead, thereby improving the yield. One idea proposed is Selective Row Partitioning (SRP), a technique which allows a single spare column to be used to repair multiple defective cells in multiple columns. This is done by selectively decoding the row address bits when generating the select signals for the column multiplexers. This logically segments the spare column allowing it to replace different columns in different partitions of the row address space. All the chips are identical, but fuses are used to customize the row decoding circuitry on a chip-by-chip basis. An implementation procedure and results are presented which show improvement in overall yield at a minimal overhead cost. Moreover, new yield-enhancing design techniques for 3-D ICs are introduced. When assembling a 3-D IC, there are several degrees of freedom including which die are stacked together, in what order, and with what rotational symmetry. This thesis describes strategies for exploiting these degrees of freedom to reduce the cost and complexity of implementing defect tolerance. One strategy is to enable asymmetric repair capability within a 3-D memory stack by exploiting the degree of freedom that the order of the die in the stack can be selected. This technique optimizes the number of fuses, and in some cases, the number of spares as well, required to implement defect tolerance. Another innovative technique is to exploit rotational symmetry of the dies to do implicit reconfiguration to implement defect tolerance. Results show that leakage power and performance overhead for defect tolerance can be significantly reduced by this technique. / text

Design techniques for heterogeneous three-dimensional (3-D) integrated circuits are developed in this thesis. Heterogeneous 3-D integration is a platform for multifunctional, high performance, and low power electronics. For the advancement of heterogeneous 3-D ICs, contactless solutions are investigated to implement inter-tier communication between tiers manufactured with disparate processes and heterogeneous technologies. Two challenges for the development of contactless inter-tier communication are addressed, the design of energy efficient, heterogeneous inductive link transceivers and the impact of crosstalk noise due to the on-chip spiral inductors. Inter-tier communication between circuits fabricated with disparate technologies requires transceivers capable of operating at dissimilar voltages. A low power transceiver design methodology is proposed exploiting the difference in the core voltage between disparate manufacturing processes in a 3-D system in package. A transceiver is designed to provide inter-tier communication between a sensing layer, designed in a commercial 0.35 Âμm process and a processing layer, designed in an advanced 65 nm process. A significant gain in the power consumed by the transceiver is shown compared to equivalent state-of-the-art prototypes, profiting by the tradeoff between the core voltage and sensing ability of the transceiver circuit in each process. Due to their wireless nature, however the use of inductive links introduces crosstalk noise due to the coupling between the on-chip inductor and on-chip interconnects in the vicinity of the inductor. The noise caused by the inductor on the power distribution network of an integrated system is explored, analysed, and modelled through electromagnetic simulations. The spatial distribution of the noise is described for several power distribution topologies to determine the preferred placement solution for the power and ground network in the vicinity of the inductor, considering the impact on other sources of noise, such as the resistive drop. Depending upon the power distribution network topology, the induced noise can be reduced up to 70% when the additional noise caused by the inductive link is considered by the routing algorithm. Additionally, a methodology utilising an analytic model is proposed for the evaluation of the crosstalk noise without resorting to electromagnetic simulations. A closed-form magnetostatic model is developed to assess the mutual inductance between the on-chip inductor and the power distribution network. Utilising the mutual inductance model, the crosstalk noise is evaluated with SPICE simulations. A signifcant benefit in speedup is achieved, up to four orders of magnitude for determining the mutual inductance and up to 4.7× for the assessment of the crosstalk noise. The accuracy of the model is within 10% of the electromagnetic simulation.

Vertical integration technologies, such as three-dimensional integration and interposers, are technologies that support high integration densities while offering shorter interconnect lengths as compared to planar integration and other packaging technologies. To exploit these advantages, however, several challenges lay across the designing, manufacturing and testing stages of integrated systems. Considering the high complexity of modern microelectronic devices and the diverse features of vertical integration technologies, this thesis sheds light on the circuit design process. New methodologies and tools are offered in order to assess and improve traditional objectives in circuit design, such as performance, power, and area for vertically integrated circuits. Interconnects on different interposer materials are investigated, demonstrating the several trade-offs between power, performance, area, and crosstalk. A backend design flow is proposed to capture the performance and power gains from the introduction of the third dimension. Emphasis is also placed on the power consumption of modern circuits due to the immense growth of battery-operated devices in the last fifteen years. Therefore, the effect of scaling the operating voltage in three-dimensional circuits is investigated as it is one of the most efficient techniques for reducing power while considering the performance of the circuit. Furthermore, a solution to eliminate timing penalties from the usage of voltage scaling technique at finer circuits granularities is also presented in this thesis.