As technology continues to scale to smaller geometries and newer dimensions (3-D), with increasingly complex manufacturing processes, the ability to reliably manufacture 100% defect-free circuitry becomes a significant challenge. While implementing additional circuitry to improve yield is economically justifiable, this thesis addresses the cost of defect tolerance by providing lower cost solutions or alternatively more defect tolerance for the same cost in state-of-the-art ICs, including three-dimensional ICs (3-D ICs). Conventional defect tolerance techniques involve incorporating redundancy into the design. This thesis introduces novel designs to maximize the utility of spare elements with minimal circuitry overhead, thereby improving the yield. One idea proposed is Selective Row Partitioning (SRP), a technique which allows a single spare column to be used to repair multiple defective cells in multiple columns. This is done by selectively decoding the row address bits when generating the select signals for the column multiplexers. This logically segments the spare column allowing it to replace different columns in different partitions of the row address space. All the chips are identical, but fuses are used to customize the row decoding circuitry on a chip-by-chip basis. An implementation procedure and results are presented which show improvement in overall yield at a minimal overhead cost. Moreover, new yield-enhancing design techniques for 3-D ICs are introduced. When assembling a 3-D IC, there are several degrees of freedom including which die are stacked together, in what order, and with what rotational symmetry. This thesis describes strategies for exploiting these degrees of freedom to reduce the cost and complexity of implementing defect tolerance. One strategy is to enable asymmetric repair capability within a 3-D memory stack by exploiting the degree of freedom that the order of the die in the stack can be selected. This technique optimizes the number of fuses, and in some cases, the number of spares as well, required to implement defect tolerance. Another innovative technique is to exploit rotational symmetry of the dies to do implicit reconfiguration to implement defect tolerance. Results show that leakage power and performance overhead for defect tolerance can be significantly reduced by this technique. / text

Nanoscale manufacturing techniques enable very high density nano fabrics but may cause orders of magnitude higher levels of defects and variability than in today‟s CMOS processes. As a result, nanoscale architectures typically introduce redundancy at multiple levels of abstractions to mask faults. Schemes such as Triple Modular Redundancy (TMR) and structural redundancies are tailored to maximize yield but can impact performance significantly. For example, due to increases in circuit fan-in and fan-out, a quadratic performance impact is often projected. In this thesis, we introduce a new class of redundancy schemes called FastTrack, designed to provide fault tolerance but without their negative impact on performance. FastTrack relies on combining non-uniform structural redundancy with uniquely biased nanoscale voters. A variety of such techniques are employed on a Wire Streaming Processor (WISP-0) implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) nanowire fabric. We show that FastTrack schemes can provide 23% higher effective yield than conventional redundancy schemes even at 10% defect rates. Most importantly, the yield improvement is achieved in conjunction with 79% lesser performance impact at 10% defect rate. This is the first redundancy scheme we are aware of to achieve such degree of fault masking without the considerable performance impact of conventional approaches. The same setup is also used to mask the effects of parameter variation. FastTrack techniques show up to 6X performance improvement compared to more traditional redundancy schemes even at higher defect rates. In the absence of defects, a FastTrack scheme can be up to 7X faster than a traditional redundancy scheme.

In this paper, a novel approach is utilized to investigate the deformation mechanisms at the microstructural level in 3D printed alloys. The complex in-situ heat treatments during 3D printing leaves a unique and complicated microstructure in the as-built 3D printed metals, particularly alloys. The microstructure is made of a hierarchical stacking of some interconnected geometrical shapes, namely meltpools, grains, and cells. These are connected to each other by boundaries that might have different element compositions, and consequently, material properties, compared to the interior region of each geometrical unit. Deformation mechanisms in this microstructure are still highly unexplored, mainly because of the challenges on the way of performing experiments at the micrometer length scale. In this work, we establish an image processing framework that directly converts the SEM images taken from the microstructure of 3D printed 316L stainless steel alloys into CAD models. The model of the complicated microstructure is then scaled up, and the scaled model is 3D printed using polymeric materials. For 3D printing these samples, two polymers with contrasting mechanical properties are used. Distribution of these two polymers mimics the arrangement of soft and stiff regions in the microstructure of 3D printed alloys. These representative samples are subjected to mechanical loads and digital image correlation is utilized to investigate the deformation mechanisms, particularly the delocalization of stress concentration and also the crack propagation, at the microstructural level of 3D printed metals. Besides experiments, computational modeling using finite element method is also performed to study the same deformation mechanisms at the microstructure of 3D printed 316L stainless steel. Our results show that the hierarchical arrangement of stiff and soft phases in 3D printed alloys delocalizes the stress concentration and has the potential to make microstructures with significantly improved damage tolerance capabilities. / Master of Science / Many researchers have studied the impacts of laser parameters on the bulk material properties of SLM printed parts; few if any have studied how these parts break at a microstructural level. In this work we show how SLM printed parts with complex microstructures including grains, meltpools, and cells, deform and break. The cellular network that occurs in some SLM printed parts leads to a multi-material hierarchical structure, with a stiff network of thin boundaries, and a bulk "matrix" of soft cell material. This leads to similar properties as some composites, whereby the stiff network of cell boundaries leads to increased damage tolerance. We show both computationally through finite element analysis, and experimentally through multi-material 3D fabrication, that the microstructure leads to increased crack length in failure, as well as lower toughness loss and strength loss in the event of a crack. Essentially, the complex nature of the formation of these parts (high heating and cooling rates from laser melting) leads to a beneficial microstructure for damage tolerance that has not been studied from this perspective before.

As complementary metal-oxide semiconductor (CMOS) technology faces more and more severe physical barriers down the path of continuously feature size scaling, innovative nano-scale devices and other post-CMOS technologies have been developed to enhance future circuit design and computation. These nanotechnologies have shown promising potentials to achieve magnitude improvement in performance and integration density. The substitution of CMOS transistors with nano-devices is expected to not only continue along the exponential projection of Moore's Law, but also raise significant challenges and opportunities, especially in the field of electronic design automation. The major obstacles that the designers are experiencing with emerging nanotechnology design include: i) the existing computer-aided design (CAD) approaches in the context of conventional CMOS Boolean design cannot be directly employed in the nanoelectronic design process, because the intrinsic electrical characteristics of many nano-devices are not best suited for Boolean implementations but demonstrate strong capability for implementing non-conventional logic such as threshold logic and reversible logic; ii) due to the density and size factors of nano-devices, the defect rate of nanoelectronic system is much higher than conventional CMOS systems, therefore existing design paradigms cannot guarantee design quality and lead to even worse result in high failure ratio. Motivated by the compelling potentials and design challenges of emerging post-CMOS technologies, this dissertation work focuses on fundamental design methodologies to effectively and efficiently achieve high quality nanoscale design. A novel programmable logic element (PLE) is first proposed to explore the versatile functionalities of threshold gates (TGs) and multi-threshold threshold gates (MTTGs). This PLE structure can realize all three- or four-variable logic functions through configuring binary control bits. This is the first single threshold logic structure that provides complete Boolean logic implementation. Based on the PLEs, a reconfigurable architecture is constructed to offer dynamic reconfigurability with little or no reconfiguration overhead, due to the intrinsic self-latching property of nanopipelining. Our reconfiguration data generation algorithm can further reduce the reconfiguration cost. To fully take advantage of such threshold logic design using emerging nanotechnologies, we also developed a combinational equivalence checking (CEC) framework for threshold logic design. Based on the features of threshold logic gates and circuits, different techniques of formulating a given threshold logic in conjunctive normal form (CNF) are introduced to facilitate efficient SAT-based verification. Evaluated with mainstream benchmarks, our hybrid algorithm, which takes into account both input symmetry and input weight order of threshold gates, can efficiently generate CNF formulas in terms of both SAT solving time and CNF generating time. Then the reversible logic synthesis problem is considered as we focus on efficient synthesis heuristics which can provide high quality synthesis results within a reasonable computation time. We have developed a weighted directed graph model for function representation and complexity measurement. An atomic transformation is constructed to associate the function complexity variation with reversible gates. The efficiency of our heuristic lies in maximally decreasing the function complexity during synthesis steps as well as the capability to climb out of local optimums. Thereafter, swarm intelligence, one of the machine learning techniques is employed in the space searching for reversible logic synthesis, which achieves further performance improvement. To tackle the high defect-rate during the emerging nanotechnology manufacturing process, we have developed a novel defect-aware logic mapping framework for nanowire-based PLA architecture via Boolean satisfiability (SAT). The PLA defects of various types are formulated as covering and closure constraints. The defect-aware logic mapping is then solved efficiently by using available SAT solvers. This approach can generate valid logic mapping with a defect rate as high as 20%. The proposed method is universally suitable for various nanoscale PLAs, including AND/OR, NOR/NOR structures, etc. In summary, this work provides some initial attempts to address two major problems confronting future nanoelectronic system designs: the development of electronic design automation tools and the reliability issues. However, there are still a lot of challenging open questions remain in this emerging and promising area. We hope our work can lay down stepstones on nano-scale circuit design optimization through exploiting the distinctive characteristics of emerging nanotechnologies. / Ph. D.