Abstract This thesis studies the level of performance achievable using today's standard IC processes in the integrated RF subcircuits of the modern GSM base station. The thesis concentrates on those circuit functions, i.e. I/Q modulators, variable gain amplifiers and frequency synthesizers, most relevant for integration in the base station environment as pinpointed by studying the receiver/transmitter architectures available today. Several RF integrated circuits have been designed, fabricated and their level of performance measured. All main circuits were fabricated in a standard double-metal double-poly 1.2 and 0.8 μm BiCMOS process. Key circuit structures and their measured properties are: 90° phase shifter with ±1° phase error with VCC = 4.5…5.5 V and T = -10…+85 °C, I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz (2.0 mm × 2.0 mm, 100 mA, 5.0 V) with LO suppression of 38 dBc and image rejection of 41 dBc, temperature compensated DC to 1.5 GHz variable gain amplifier (1.15 mm × 2.00 mm, 100 mA, 5.0 V) with a linear 50 dB gain adjustment range, maximum gain of 18.5 dB and gain variation of 1 dB up to 700 MHz over the whole operating conditions range of VCC = 4.5…5.5 V and T = -10…+85 °C, a complete bipolar semicustom synthesizer (90…122 mA, 5.0 V) and two complete full-custom BiCMOS synthesizer chips including all building blocks of a PLL-based synthesizer except for the voltage controlled oscillator and the loop filter. The synthesizers include circuit structures such as ∼2 GHz multi-modulus divider and low-noise programmable phase detector/charge pump (18.7 pA/√Hz at Iout = 500 μA) and have an exemplar phase noise performance of -110 dBc/Hz at 200 kHz offset. One of the main problems of the integer-N PLL based synthesizer when used in a multichannel telecommunications system is the level of spurious signals at the output, when the synthesizer is optimised for fast frequency switching. Therefore, a method using only two current pulses to make the frequency step response of the loop faster, thus allowing a narrower loop bandwidth to be used for additional spur suppression, is proposed. The operation of the proposed speed-up method is analysed mathematically and verified by measurements of an existing RF-IC synthesizer operating at 800 MHz. Measurements show that simple current pulses can be used to speed up the channel switching of a practical RF synthesizer having a frequency step time in the tens of μs range. In the example, a 7.65 MHz frequency step was made seven times faster using the proposed method.

Avec la croissance actuelle du marché des applications de transfert de données multimédia à très haut débit, les bandes de fréquences autour de 60 GHz sont une nouvelle alternative promettant des performances intéressantes en terme de débits mais soulèvent des défis techniques et technologiques au niveau des architectures et circuits. C'est dans ce cadre que s'inscrit cette thèse, qui propose une approche multi bande impulsionnelle MBOOK avec un récepteur à détection d'énergie, et qui analyse plus spécifiquement les verrous au niveau de l'émetteur. L'étude du canal de propagation à 60 GHz, basée sur les modèles de canaux du standard IEEE 802.15.3c, a permis de démontrer la potentialité de cette architecture et permet d'atteindre des débits de 2 Gbps à 2metres dans un environnement de type résidentiel. Le dimensionnement de l'architecture ainsi que des performances des principaux blocs ont conduit à plusieurs possibilités pour l'architecture de l'émetteur MBOOK à 60 GHz. Les critères ont été d'assurer un compromis performances, consommation. Une étude approfondie sur l'étude des imperfections de certains blocs critiques et l'impact sur l'impulsion transmise, et donc sur les performances du système ont été établies. Le banc de filtres, nécessaire à l'émission et à la réception, représente l'un des verrous, et nous proposons une solution de filtrage à base de lignes couplées. L'étude des solutions de génération d'impulsions, des étages de commutation, et des étages d'amplification de l'émetteur sont détaillées et discutées dans les deux derniers chapitres / With the current increasing market request concerning high speed data rates applications, the 60 GHz frequency bands seems to be one of the new promising alternatives for high data rate wireless communications. In this context, the development of new systems operating at these frequencies becomes a very attractive research subject. This study focuses on nomadic systems offering high data and reconfigurable rates, low complexity, low power consumption for short communications. One of the important tasks in the millimetre wave architecture design is to consider the channel propagation characteristics simultaneously with the technological performance of integrated circuits and antennas. This requires a co-design of the entire system. Therefore, we begun by studying the characteristics of the channel propagation channel at 60GHz according to the IEEE 802.15.3c and IEEE 802.11.ad models. This PHD thesis proposes a new transceiver architecture based on multi-band impulse mode, with On Off Keying modulation schema and non coherent receiver. This architecture is dedicated to nomadic systems offering high data and reconfigurable rates, low complexity, low power consumption for short communications. Analysis and performances for the proposed architecture are presented. More than 2 Gbps at 2 m are obtained. The imperfections of some critical blocks and their impact on the transmitted pulses were analysed and thus the performance of the system has been established. The potentiality of microstrip band pass filter bank presenting a constant relative bandwidth and reasonable insertion losses is presented in this study. The study of pulse generation solutions, switchers, amplification stages and antennas are detailed and discussed in the last two chaptersconstant relative bandwidth and reasonable insertion losses is presented in this study.The study of pulse generation solutions, switchers, amplification stages and antennas are detailed and discussed in the last two chapters.

The radio frequency (RF) spectrum as a natural resource is severely under-utilized over time and space due to an inefficient licensing framework. As a result, in-creasing cellular and wireless network usage is placing significant demands on the licensed spectrum. This has led to the development of cognitive radios, software defined radios and mm-wave radios. Cognitive radios (CRs) enable more efficient spectrum usage over a wide range of frequencies and hence have emerged as an effective solution to handle huge network demands. They promise versatility, flex-ability and cognition which can revolutionize communications systems. However, they present greater challenges to the design of radio frequency (RF) front-ends. Instead of a narrow-band front-end optimized and tuned to the carrier frequency of interest, cognitive radios demand front-ends which are versatile, configurable, tun-able and capable of transmitting and receiving signals with different bandwidths and modulation schemes. The primary purpose of this thesis is to design a re-configurable, wide-band and low phase-noise fast settling frequency synthesizer for cognitive radio applications. Along with frequency generation, an area efficient multi-band low noise amplifier (LNA) with integrated built-in-self-test (BIST) and a strong immunity to interferers has also been proposed and implemented for these radios. This designed LNA relaxes the specification of harmonic content in the synthesizer output. Finally some preliminary work has also been done for mm-wave (V-band) frequency synthesis. The Key Contributions of this thesis are: A frequency synthesizer, based on a type-2, third-order Phase Locked Loop (PLL), covering a frequency range of 0.1-5.4 GHz, is implemented using a 0.13 µm CMOS technology. The PLL uses three voltage controlled oscillators (VCOs) to cover the whole range. It is capable of switching between any two frequencies in less than 3 µs and has phase noise values, compatible with most communication standards. The settling of the PLL in the desired state is achieved in dynamic multiple steps rather than traditional single step settling. This along with other circuit techniques like a DAC-based discriminator aided charge pump, fast acquisition pulse-clocked based PFD and timing synchro-negation is used to obtain a significantly reduced settling time A single voltage controlled LC-oscillator (LC-VCO) has been designed to cover a wide range of frequencies (2.0-4.1 GHz) using an area efficient and switch-able multi-tap inductor and a capacitor bank. The switching of the multi-tap inductor is done in the most optimal manner so as to get good phase-noise at the output. The multi-tap inductor provides a significant area advantage, and in spite of a degraded Q, provides an acceptable phase noise of -123 dBc/Hz and -113 dBc/Hz at an offset of 1 MHz at carrier frequencies of 2 and 4 GHz, respectively. Implemented in a 0.13 µm CMOS technology, the oscillator with ≈ 69 % tuning range, occupies an active area of only 0.095 mm2. An active inductor based noise-filter has been proposed to improve the phase-noise performance of the oscillator without much increase in the area. A variable gain multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (0.8 GHz to 2.4 GHz) using an area efficient switchable-π network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip Built-in-Self-Test (BIST) circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (I I P3) ranges from -15 dBm to 0 dBm. Implemented in a 0.13 µm CMOS technology, the LNA occupies an active area of about 0.29 mm2. Three different types of VCOs (stand-alone LC VCO, push-push VCO and a ring oscillator based VCO) for generating mm-wave frequencies have been implemented using 65-nm CMOS technology and their measured results have been analyzed