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A 1.8V 12bits 100-MS/s Pipelined Analog-to-Digital Converter

The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter.
In this thesis, the circuits are designing with TSMC.18 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0807107-102239
Date07 August 2007
CreatorsChen, Bo-Hua
ContributorsChia-Hsiung Kao, Ko-Chi Kuo, Shiann-Rong Kuang
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageEnglish
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0807107-102239
Rightsnot_available, Copyright information available at source archive

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