In nanometer technologies, process variation control and low power have emerged as
the first order design goal after high performance. Process variations cause high variability
in performance and power consumption of an IC, which affects the overall yield. Short
channel effects (SCEs) deteriorate the MOSFET performance and lead to higher leakage
power. Double gate devices suppress SCEs and are potential candidates for replacing Bulk
technology in nanometer nodes. Threshold voltage control in planar asymmetric double
gate transistor (IGFET) using a fourth terminal provides an effective means of combating
process variations and low power design. In this thesis, using various case studies, we
analyzed the suitability of IGFET for variation control and low power design. We also
performed an extensive comparison between IGFET and Bulk for reducing variability, improving
yield and leakage power reduction using power gating. We also proposed a new
circuit topology for IGFET, which on average shows 33.8 percent lower leakage and 34.9 percent lower
area at the cost of 2.8 percent increase in total active mode power, for basic logic gates. Finally,
we showed a technique for reducing leakage of minimum sized devices designed using new
circuit topology for IGFET.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-08-8488 |
| Date | 2010 August 1900 |
| Creators | Singh, Amrinder |
| Contributors | Hu, Dr. Jiang |
| Source Sets | Texas A and M University |
| Language | en_US |
| Detected Language | English |
| Type | thesis, text |
| Format | application/pdf |
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