Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed.
An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems.
ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology.
Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.
| Identifer | oai:union.ndltd.org:IISc/oai:etd.ncsi.iisc.ernet.in:2005/3167 |
| Date | January 2012 |
| Creators | Chaturvedi, Vikram |
| Contributors | Amrutur, Bharadwaj |
| Source Sets | India Institute of Science |
| Language | en_US |
| Detected Language | English |
| Type | Thesis |
| Relation | G25552 |
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