In an effort to lower interconnect time delays and power dissipation in highly integrated logic and memory nanoelectronic products, numerous changes in the materials and processes utilized to fabricate the interconnect have been made in the past decade. Chief among these changes has been the replacement of aluminum (Al) by copper (Cu) as the interconnect metal and the replacement of silicon dioxide (SiO2) by so called low dielectric constant (low-k) materials as the insulating interlayer dielectric (ILD). Cu/low-k structure significantly decreases the RC delay compared with the traditional interconnect (Al/SiO₂). Therefore, the implementation of low-k dielectric in Cu interconnect structures has become one of the key subjects in the microelectronics industry. Incorporation of pores into the existing low-k dielectric is a favorable approach to achieve ultra low-k ILD materials.
To bring memory and logic closer together is an effective approach to remove the latency constraints in metal interconnects. The resistive random access memories (RRAM) technology can be integrated into a complementary metal-oxide-semiconductor (CMOS) metal interconnect structure using standard processes employed in back-end-of-line (BEOL) interconnect fabrication. Based on this premise, the study of this thesis aims at assessing a possible co-integration of resistive switching (RS) cells with current BEOL technology. In particular, the issue is whether RS can be realized with porous dielectrics, and if so, what is the electrical characterization of porous low-k/Cu interconnect-RS devices with varying percentages of porosity, and the diffusive and drift transport mechanism of Cu across the porous dielectric under high electric fields.
This work addresses following three areas:
1. Suitability of porous dielectrics for resistive switching memory cells. The porous dielectrics of various porosity levels have been supplied for this work by Intel Inc. In course of the study, it has been found that Cu diffusion and Cu+ ion drift in porous materials can be significantly different from the corresponding properties in non-porous materials with the same material matrix.
2. Suitability of ruthenium as an inert electrode in resistive switching memory cells. Current state-of-the-art thin Cobalt (Co)/Tantalum Nitride (TaN) bilayer liner with physical vapor deposited (PVD) Cu-seed layer has been implemented for BEOL Cu/low-k interconnects. TaN is used for the barrier and Co is used to form the liner as well as promoting continuity for the Cu seed. Also, the feasibility of depositing thin CVD ruthenium (Ru) liners in BEOL metallization schemes has been evaluated. For this study, Ru is used as a liner instead of Ta or Co in BEOL interconnects to demonstrate whether it can be a potential candidate for replacing PVD-based TaN/Ta(Co)/Cu low-k technology. In this context, it is of interest to investigate how Ru would perform in well-characterized RS cell, like Cu/TaOx/Ru, given the fact that Cu/TaOx/Pt device have been proven to be good CBRAM device due to its excellent unipolar and bipolar switching characteristics, device performance, retention, reliability. If Cu/TaOx/Ru device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end.
3. Potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells. The BEOL reliability is tied to time dependent failure that occurs inside dielectric between metal lines. Assessing the suitability of covalent dielectrics for back-end metallization is therefore an interesting topic. TDDB measurements have been performed on pure covalent materials, low-k dielectric MIM and MI-semiconductor (MIS) devices supplied by Intel Inc. / Master of Science / While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel types of non-volatile memories, such as resistive-switching memories, have recently been of interest to both industry and academia. Resistive switching memory is being considered for next-generation non-volatile memory due to relatively high switching speed, high scalability, low power consumption, good retention and simple structure. Additionally, these twoterminal devices operate by changing resistance from high resistance OFF-state (HRS) to low resistance ON-state (LRS) in response to applied voltage or current due to the formation and rupture of a conductive filament. In particular, Conductive Bridging Random Access Memory (CBRAM), also referred as Programmable Metallization Cell (PMC), is a promising candidate for a resistive memory device due to its highly scalable and low-cost technology. Currently, the interconnect RC scaling methods have reached their limits and there is an urgent need for alternative ways to reduce or remove the latency constraints in CMOS low-k/Cu interconnect. One method is building CBRAM directly into a low-k/Cu interconnects to reduce the latency in connectivity constrained computational devices and the chip’s footprint by stacking memory on top of logic circuits. This is possible since the Cu metal lines and low-k/Cu interconnect already prefigure a potential RS device.
This work addresses three areas: Firstly, the suitability of porous dielectrics for resistive switching memory cells. Secondly, the suitability of ruthenium as an inert electrode in resistive switching memory cells. If Ru resistive memory device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end-of-line (BEOL). Thirdly, the potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells.
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/78172 |
| Date | 16 January 2017 |
| Creators | Fan, Ye |
| Contributors | Electrical and Computer Engineering, Orlowski, Mariusz Kriysztof, Heremans, Jean J., Lu, Guo Quan |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Language | en_US |
| Detected Language | English |
| Type | Thesis, Text |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
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