This thesis presents a fully differential 9-bit current-mode successive approximation (SAR) ADC. The circuit is designed in 0.18 um technology with 1.8 V supply voltage and has a current draw on 472 uA. The ADC has a sampling frequency on 50 MHz and has a maximum ENOB on 8.42 bit. Because of non-linearity will ENOB be input frequency dependent and degrade to 6.87 bit.The design is based on conventional current-mode SAR ADC operation, but with a new comparator design and time interleaving. Time interleaving is used to increase the sampling frequency 10 times.The circuit needs a high degree of matching to work properly. Sub-threshold operation in several current sources gives a high degree of uncertainty in the current value. Thus several calibration circuits are presented, but are not implemented.
Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:ntnu-18820 |
Date | January 2012 |
Creators | Eilertsen, Bård Egil |
Publisher | Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, Institutt for elektronikk og telekommunikasjon |
Source Sets | DiVA Archive at Upsalla University |
Language | English |
Detected Language | English |
Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
Format | application/pdf |
Rights | info:eu-repo/semantics/openAccess |
Page generated in 0.0012 seconds