CPU-memory bottleneck is a widely recognized problem. It is known that majority of high performance computing (HPC) database systems are configured with large memories and dedicated to process specific workloads like weather prediction, molecular dynamic simulations etc. My research on optimal address mapping improves the memory performance by increasing the channel and bank level parallelism. In an another research direction, I proposed and evaluated adaptive page migration techniques that obviates the need for offline analysis of an application to determine page migration strategies. Furthermore, I explored different migration strategies like reverse migration, sub page migration that I found to be beneficial depending on the application behavior. Ideally, page migration strategies redirect the demand memory traffic to faster memory to improve the memory performance. In my third contribution, I worked and evaluated a memory-side accelerator to assist the main computational core in locating the non-zero elements of a sparse matrix that are typically used in scientific, machine learning workloads on a low-power embedded system configuration. Thus my contributions narrow the speed-gap by improving the latency and/or bandwidth between CPU and memory.
| Identifer | oai:union.ndltd.org:unt.edu/info:ark/67531/metadc1873542 |
| Date | 12 1900 |
| Creators | Adavally, Shashank |
| Contributors | Kavi, Krishna, Gulur, Nagendra, Fu, Song, Zhao, Hui, Jayasena, Nuwan |
| Publisher | University of North Texas |
| Source Sets | University of North Texas |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
| Format | xii, 130 pages, Text |
| Rights | Public, Adavally, Shashank, Copyright, Copyright is held by the author, unless otherwise noted. All rights Reserved. |
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