Future communication systems require low latency Fast Fourier transform (FFT)computation with a small cost of area. In this study, a memory-based FFT processorwith low latency is designed. To reduce latency and maintain constant outputsample rate, a scheduling method suitable for input sample rate and clock rateis used in the radix-2 butterfly processing elements. The scheduling scheme employsa combination of ASAP and ALAP scheduling strategies. A mathematicalexpression that models FFT’s latency is given. The size of FFT, the input samplerate, and the number of processing elements are the input parameters of the expression.The effect of using pipelined processing element is also studied. Lastly,the proposed low latency design is compared with other low-latency FFT designs.The result shows that, in the 4G LTE application scenario, our memory-based designcan do the FFT computations faster with a small area.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-198468 |
| Date | January 2023 |
| Creators | Tan, Xiangbin, Negash, Tadesse Hadush |
| Publisher | Linköpings universitet, Institutionen för systemteknik |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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