Mak Wing-sum. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaf [68]). / Abstracts in English and Chinese. / List of Figures --- p.I / List of Tables --- p.III / ACKNOWLEDGMENTS / ABSTRACT / Chapter Chapter I --- Introduction / Chapter 1.1 --- Introduction - Low Power --- p.I-1 / Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1 / Chapter 1.2.1 --- Static Power Dissipation --- p.I-2 / Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5 / Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8 / Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10 / Chapter 1.4 --- Objective of the Project --- p.I-10 / Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic / Chapter 2.1 --- Low Power Design --- p.II-12 / Chapter 2.2 --- Adiabatic Switching --- p.II-12 / Chapter 2.3 --- Adiabatic Logic --- p.II-14 / Chapter 2.4 --- History of Adiabatic Logic --- p.II-17 / Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter / Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18 / Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20 / Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22 / Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23 / Chapter Chapter IV --- Power Clock Generator / Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24 / Chapter 4.2 --- Power Clock Generator / Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV / Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27 / Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier / Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32 / Chapter 5.2 --- Structure of Multiplier --- p.V-34 / Chapter Chapter VI --- Simulations / Chapter 6.1 --- AqsCMOS Inverter / Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38 / Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39 / Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI / Chapter 6.2 --- Power Clock Generator --- p.VI -42 / Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45 / Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46 / Chapter ChapterVII --- evaluations / Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51 / Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus / Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54 / Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55 / Chapter 7.2.3 --- Input Current Measurement --- p.VII -58 / Chapter 7.3 --- Power Measurement --- p.VII -63 / Chapter Chapter VIII --- Conclusions and Fiirthfr Developments / Chapter 8.1 --- Conclusions --- p.VIII -65 / Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65 / Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65 / Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66 / Chapter 8.2 --- Further Development --- p.VIII -66 / Appendix I micro-photography of aqscmos multiplier / Appendix II micro-Photography of CMOS multiplier / Appendix III micro-photography of AqsCMOS inverter chain testing modules / Appendix IV power - meter simulation approach / Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers / Reference
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_323251 |
| Date | January 2000 |
| Contributors | Mak, Wing-sum., Chinese University of Hong Kong Graduate School. Division of Electronic Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, iii, iii, 67, [7] leaves : ill. (some col.) ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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