Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 51-53). Also available on the World Wide Web.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Missouri-Columbia, 2003. / Typescript. Vita. Includes bibliographical references (leaves 111-118). Also available on the Internet.

Thesis (Ph. D.)--University of Missouri-Columbia, 2003. / Typescript. Vita. Includes bibliographical references (leaves 111-118). Also available on the Internet.

Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2007. / Includes bibliographical references (p. 117-121).

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

Mak Wing-sum. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaf [68]). / Abstracts in English and Chinese. / List of Figures --- p.I / List of Tables --- p.III / ACKNOWLEDGMENTS / ABSTRACT / Chapter Chapter I --- Introduction / Chapter 1.1 --- Introduction - Low Power --- p.I-1 / Chapter 1.2 --- Power Consumption in cmos Circuit --- p.I-1 / Chapter 1.2.1 --- Static Power Dissipation --- p.I-2 / Chapter 1.2.2 --- Dynamic Power Dissipation --- p.I-5 / Chapter 1.2.3 --- Short Circuit Power Dissipation --- p.I-8 / Chapter 1.3 --- Total Power Consumption of a CMOS Circuit --- p.I-10 / Chapter 1.4 --- Objective of the Project --- p.I-10 / Chapter CHAPTER II --- Background : Low Power Electronic - Adiabatic Logic / Chapter 2.1 --- Low Power Design --- p.II-12 / Chapter 2.2 --- Adiabatic Switching --- p.II-12 / Chapter 2.3 --- Adiabatic Logic --- p.II-14 / Chapter 2.4 --- History of Adiabatic Logic --- p.II-17 / Chapter CHAPTER III --- Adiabatic Quasi-Static CMOS Inverter / Chapter 3.1 --- Building Block of AqsCMOS Logic --- p.III -18 / Chapter 3.2.1 --- AqsCMOS Inverter --- p.III -20 / Chapter 3.2.2 --- Diodes of AqsCMOS Inverter --- p.III -22 / Chapter 3.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.III -23 / Chapter Chapter IV --- Power Clock Generator / Chapter 4.1 --- Inductor - Capacitor Oscillator --- p.IV -24 / Chapter 4.2 --- Power Clock Generator / Chapter 4.2.1 --- Structure of Power Clock Generator --- p.IV / Chapter 4.2.2 --- power Consumption of Power Clock Generator --- p.IV -27 / Chapter Chapter V --- Adiabatic QuasI-Static CMOS Multiplier / Chapter 5.1 --- Baugh - Wooley Multiplier --- p.V-32 / Chapter 5.2 --- Structure of Multiplier --- p.V-34 / Chapter Chapter VI --- Simulations / Chapter 6.1 --- AqsCMOS Inverter / Chapter 6.1.1 --- Logic Alignment of AqsCMOS Inverter --- p.VI -38 / Chapter 6.1.2 --- Practical Implementation of AqsCMOS Inverter --- p.VI -39 / Chapter 6.1.3 --- Pipeline Clocking of AqsCMOS Inverter Chain --- p.VI / Chapter 6.2 --- Power Clock Generator --- p.VI -42 / Chapter 6.3 --- AqsCMOS Pipeline Multiplier --- p.VI -45 / Chapter 6.3.1 --- power estimation of multiplier --- p.VI -46 / Chapter ChapterVII --- evaluations / Chapter 7.1 --- Testing Modules of AqsCMOS Inverter Chain --- p.VII -51 / Chapter 7.2 --- Evaluation of AqsCMOS Multiplier Testing Modulus / Chapter 7.2.1 --- Multiplier Chips Implementation --- p.VII -54 / Chapter 7.2.2 --- AQSCMOS Vs CMOS MULTIPLIER --- p.VII -55 / Chapter 7.2.3 --- Input Current Measurement --- p.VII -58 / Chapter 7.3 --- Power Measurement --- p.VII -63 / Chapter Chapter VIII --- Conclusions and Fiirthfr Developments / Chapter 8.1 --- Conclusions --- p.VIII -65 / Chapter 8.1.1 --- AqsCMOS Inverter --- p.VIII -65 / Chapter 8.1.2 --- Power Clock Generator --- p.VIII -65 / Chapter 8.1.3 --- AQSCMOS MULTIPLIER --- p.VIII -66 / Chapter 8.2 --- Further Development --- p.VIII -66 / Appendix I micro-photography of aqscmos multiplier / Appendix II micro-Photography of CMOS multiplier / Appendix III micro-photography of AqsCMOS inverter chain testing modules / Appendix IV power - meter simulation approach / Appendix V Measurement Setting of AqsCMOS & CMOS Multipliers / Reference

by Kelvin Cheung Ka Wai. / Thesis submitted in: June 1997. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references. / ACKNOWLEDGEMENTS --- p.i / ABSTRACT --- p.ii / TABLE OF CONTENTS --- p.iii / LIST OF FIGURES --- p.vi / TIST OF TABLES --- p.viii / Chapter 1. --- INTRODUCTION --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Objective --- p.1-1 / Chapter 1.3 --- Static CMOS Logic and Dynamic Logic --- p.1-1 / Chapter 1.3.1 --- static CMOS logic circuit --- p.1-1 / Chapter 1.3.2 --- Dynamic logic --- p.1-2 / Chapter 1.4 --- Power Consumption in Static CMOS Integrated Circuit --- p.1-4 / Chapter 1.4.1 --- Static power dissipation --- p.1 -4 / Chapter 1.4.2 --- Dynamic power dissipation --- p.1 -6 / Chapter 1.4.2.1 --- Short circuit current --- p.1 -6 / Chapter 1.4.2.2 --- Charging and discharging of load capacitances --- p.1-6 / Chapter 1.4.2.3 --- Total power consumption --- p.1-8 / Chapter 1.5 --- Adiabatic Logic --- p.1-8 / Chapter 1.5.1 --- Low power electronics --- p.1-8 / Chapter 1.5.2 --- History of adiabatic logic --- p.1 -9 / Chapter 1.6 --- Resources --- p.1-10 / Chapter 1.6.1 --- Computing instrument --- p.1-10 / Chapter 1.6.2 --- CAD tools --- p.1-10 / Chapter 1.6.3 --- Fabrication --- p.1-11 / Chapter 1.7 --- Organisation of the Thesis --- p.1-11 / Chapter 2. --- BACKGROUND THEORIES --- p.2-1 / Chapter 2.1 --- Limit of energy dissipation --- p.2-1 / Chapter 2.2 --- Reversible Electronics --- p.2-1 / Chapter 2.2.1 --- Reversibility --- p.2-1 / Chapter 2.2.2 --- Adiabatic Switching --- p.2-3 / Chapter 2.2.2.1 --- Conventional Charging --- p.2-3 / Chapter 2.2.2.2 --- Adiabatic Charging --- p.2-4 / Chapter 2.2.3 --- Reversible devices --- p.2-5 / Chapter 2.3 --- Compatibility to CMOS Logic --- p.2-6 / Chapter 3. --- ADIABATIC QUASI-STATIC CMOS --- p.3-1 / Chapter 3.1 --- Swinging between 0 and 1 by Harmonic Motion --- p.3-1 / Chapter 3.1.1 --- Starting from a simple pendulum --- p.3-1 / Chapter 3.1.2 --- Inductor-capacitor oscillator --- p.3-2 / Chapter 3.2 --- Redistribution of Charge --- p.3-3 / Chapter 3.3 --- Adiabatic Quasi-static Logic --- p.3-4 / Chapter 3.3.1 --- False reversible inverter --- p.3-4 / Chapter 3.3.2 --- Adiabatic inverter --- p.3-5 / Chapter 3.3.3 --- Effective capacitance --- p.3-7 / Chapter 3.3.4 --- Logic alignment --- p.3-8 / Chapter 3.3.5 --- Cascading the adiabatic inverters --- p.3-10 / Chapter 3.3.5.1 --- Compensated cascading --- p.3-10 / Chapter 3.3.5.2 --- Balanced cascading --- p.3-11 / Chapter 3.4 --- Frequency Control --- p.3-12 / Chapter 3.5 --- Compatibility of AqsCMOS with Static CMOS Logic --- p.3-13 / Chapter 4. --- ADIABATIC QUASI-STATIC CMOS INVERTERS --- p.4-1 / Chapter 4.1 --- Design --- p.4-1 / Chapter 4.1.1 --- Realisation of current direction control device --- p.4-1 / Chapter 4.1.2 --- Implementation of AqsCMOS inverter by current direction control device --- p.4-2 / Chapter 4.1.3 --- Layout --- p.4-3 / Chapter 4.1.3.1 --- Horizontal Transistor Diode --- p.4-3 / Chapter 4.1.3.2 --- Transistor pair --- p.4-9 / Chapter 4.2 --- Capacitance Calculation --- p.4-9 / Chapter 4.2.1 --- Non-switching device --- p.4-10 / Chapter 4.2.2 --- Switching device --- p.4-11 / Chapter 4.3 --- Clocking Scheme --- p.4-13 / Chapter 4.4 --- Energy Loss of AqsCMOS inverter --- p.4-14 / Chapter 5. --- ADIABATIC CLOCKS GENERATOR --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Full Adiabatic Clocks Generator --- p.5-1 / Chapter 5.2.1 --- Sizes of the transistors used --- p.5-2 / Chapter 5.2.2 --- Energy consumption of full adiabatic clocks generator --- p.5-3 / Chapter 5.3 --- Half Adiabatic Clocks Generator --- p.5-4 / Chapter 5.3.1 --- Transistor sizing --- p.5-5 / Chapter 5.3.2 --- Energy consumption of the half adiabatic clock generator --- p.5-5 / Chapter 5.3.3 --- Weakness of the half adiabatic clocks generator --- p.5-6 / Chapter 5.4 --- Automatic Adiabatic Clocks Generator --- p.5-6 / Chapter 5.4.1 --- Operation of automatic adiabatic clocks generator --- p.5-7 / Chapter 5.4.2 --- Energy consumption of automatic adiabatic clocks generator --- p.5-9 / Chapter 6. --- EVALUATION --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Simulation Results --- p.6-1 / Chapter 6.2.1 --- Adiabatic clocks generators --- p.6-1 / Chapter 6.2.2 --- Adiabatic quasi-static CMOS inverters --- p.6-4 / Chapter 6.2.2.1 --- Functional evaluation --- p.6-4 / Chapter 6.2.2.2 --- Performance evaluation --- p.6-6 / Chapter 6.3 --- Test Circuit - Pendulum --- p.6-8 / Chapter 6.3.1 --- Layout --- p.6-8 / Chapter 6.3.2 --- Test circuit of pendulum --- p.6-10 / Chapter 6.3.3 --- Module 1 - Full adiabatic clocks generator (fclk) --- p.6-11 / Chapter 6.3.4 --- Module 2 - Half adiabatic clocks generator (hclk) --- p.6-13 / Chapter 6.3.5 --- Module 3 to 5- Adiabatic inverter chains --- p.6-14 / Chapter 6.3.5.1 --- DC characteristics --- p.6-14 / Chapter 6.3.5.2 --- AC characteristics --- p.6-14 / Chapter 6.3.6 --- Power dissipation --- p.6-17 / Chapter 7 --- CONCLUSIONS --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Design --- p.7-1 / Chapter 7.2.1 --- Adiabatic quasi-static CMOS logic --- p.7-1 / Chapter 7.2.2 --- Adiabatic quasi-static CMOS inverters --- p.7-2 / Chapter 7.2.3 --- Adiabatic clocks generator --- p.7-2 / Chapter 7.3 --- Function --- p.7-3 / Chapter 7.4 --- Power Dissipation --- p.7-3 / Chapter 7.5 --- Discussion --- p.7-3 / Chapter 7.6 --- Further Development --- p.7-3 / Chapter 7.7 --- Conclusion --- p.7-4 / Chapter 8. --- REFERENCES --- p.8-1 / APPENDIX I TABLE OF PTN LAYOUT PENDULUM --- p.I-1 / APPENDIX II PHOTOGRAPHS OF PENDULUM --- p.II-1

by Cheng Wang Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 108-111). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgments --- p.v / Contents --- p.vii / List of Tables --- p.xiii / List of Figures --- p.xiv / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Technical Challenges of CMOS RF Design --- p.2 / Chapter 1.3 --- General Background --- p.2 / Chapter 1.3.1 --- Bipolar and CMOS Mixers --- p.4 / Chapter 1.4 --- Research Goal --- p.4 / Chapter 1.5 --- Thesis Outline --- p.5 / Chapter Chapter2 --- RF Fundamentals --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Frequency Translation --- p.6 / Chapter 2.3 --- Conversion Gain --- p.8 / Chapter 2.4 --- Linearity --- p.8 / Chapter 2.4.1 --- 1-dB Compression Point --- p.11 / Chapter 2.4.2 --- Third Intercept Point (IP3) --- p.11 / Chapter 2.5 --- Dynamic Range (DR) --- p.13 / Chapter 2.5.1 --- Spurious-Free Dynamic Range (SFDR) --- p.13 / Chapter 2.5.2 --- Blocking Dynamic Range (BDR) --- p.14 / Chapter 2.6 --- Blocking and Desensitization --- p.15 / Chapter 2.7 --- Port-to-Port Isolation --- p.15 / Chapter 2.8 --- Single-Balanced and Double-Balanced Mixers --- p.16 / Chapter 2.9 --- Noise --- p.16 / Chapter 2.9.1 --- Noise in the Local Oscillator --- p.17 / Chapter 2.9.2 --- Noise Figure --- p.18 / Chapter Chapter3 --- Downconversion Mixer --- p.19 / Chapter 3.1 --- Introduction --- p.19 / Chapter 3.2 --- Review of Mixer Topology --- p.19 / Chapter 3.2.1 --- Square-Law Mixer --- p.20 / Chapter 3.2.2 --- CMOS Gilbert Cell --- p.21 / Chapter 3.2.3 --- Potentiometric Mixer --- p.22 / Chapter 3.2.4 --- Subsampling Mixer --- p.23 / Chapter Chapter4 --- Proposed Downconversion Mixer --- p.24 / Chapter 4.1 --- Analysis of Proposal Mixer --- p.24 / Chapter 4.2 --- Current Folded Mirror Mixer --- p.24 / Chapter 4.2.1 --- Operating Principle --- p.25 / Chapter 4.2.2 --- Large Signal Analysis --- p.26 / Chapter 4.2.3 --- Small Signal Analysis --- p.29 / Chapter 4.3 --- Current Mode Mixer --- p.32 / Chapter 4.3.1 --- Operating Principle --- p.33 / Chapter 4.3.2 --- Large Signal Analysis --- p.33 / Chapter 4.3.3 --- Small Signal Analysis --- p.34 / Chapter 4.3.4 --- V-I Converter --- p.36 / Chapter 4.3.4.1 --- Equation Analysis --- p.37 / Chapter 4.4 --- Second Order Effects --- p.38 / Chapter 4.4.1 --- Device Mismatch --- p.38 / Chapter 4.4.2 --- Body Effect --- p.39 / Chapter 4.5 --- Single-ended to Differential-ended converter --- p.39 / Chapter 4.6 --- Output Buffer Stage --- p.40 / Chapter 4.7 --- Noise Theory --- p.41 / Chapter 4.7.1 --- SSB and DSB Noise Figure --- p.42 / Chapter 4.7.2 --- Noise Figure --- p.43 / Chapter Chapter5 --- Simulation Results --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Current Folded Mirror Mixer --- p.44 / Chapter 5.2.1 --- Conversion Gain --- p.45 / Chapter 5.2.2 --- Linearity --- p.46 / Chapter 5.2.2.1 --- 1dB Compression Point and IIP3 --- p.49 / Chapter 5.2.3 --- Output Buffer Stage --- p.49 / Chapter 5.3 --- Current Mode Mixer --- p.51 / Chapter 5.3.1 --- Conversion Gain --- p.51 / Chapter 5.3.2 --- Linearity --- p.52 / Chapter 5.3.2.1 --- 1-dB Compression Point and IIP3 --- p.52 / Chapter 5.3.3 --- Output Buffer Stage --- p.53 / Chapter 5.3.4 --- V-I Converter --- p.54 / Chapter 5.4 --- Single-ended to Differential-ended Converter --- p.55 / Chapter Chapter6 --- Layout Consideration --- p.57 / Chapter 6.1 --- Introduction --- p.57 / Chapter 6.2 --- CMOS transistor Layout --- p.57 / Chapter 6.3 --- Resistor Layout --- p.59 / Chapter 6.4 --- Capacitor Layout --- p.60 / Chapter 6.5 --- Substrate Tap --- p.62 / Chapter 6.6 --- Pad Layout --- p.63 / Chapter 6.7 --- Analog Cell Layout --- p.64 / Chapter Chapter7 --- Measurements --- p.65 / Chapter 7.1 --- Introduction --- p.65 / Chapter 7.2 --- Downconversion mixer --- p.66 / Chapter 7.3 --- PCB Layout --- p.66 / Chapter 7.4 --- Test Setups --- p.68 / Chapter 7.4.1 --- Measurement Setup for S-Parameter --- p.68 / Chapter 7.4.2 --- Measurement Setup for 1-dB Compression Point and IIP3 --- p.70 / Chapter 7.5 --- Measurement Result of the Current Folded Mirror Mixer --- p.72 / Chapter 7.5.1 --- S-Parameter Measurement --- p.75 / Chapter 7.5.2 --- Conversion Gain and the Effect of the IF Variation --- p.77 / Chapter 7.5.3 --- 1-dB Compression Point --- p.78 / Chapter 7.5.4 --- IIP3 --- p.79 / Chapter 7.5.5 --- LO Power Effect to the Mixer --- p.81 / Chapter 7.5.6 --- Performance Summaries of the Current Folded Mirror Mixer --- p.82 / Chapter 7.5.7 --- Discussion --- p.83 / Chapter 7.6 --- Measurement Result of the Current Mode Mixer --- p.84 / Chapter 7.6.1 --- S-Parameter Measurement --- p.87 / Chapter 7.6.2 --- Conversion Gain and the Effect of the IF Variation --- p.89 / Chapter 7.6.3 --- 1-dB Compression Point --- p.90 / Chapter 7.6.4 --- IIP3 --- p.91 / Chapter 7.6.5 --- LO Power Effect to the Mixer --- p.93 / Chapter 7.6.6 --- Performance Summaries of the Current Mode Mixer --- p.94 / Chapter 7.6.7 --- Discussion --- p.95 / Chapter 7.7 --- Measurement Result of the Single-ended to Differential-ended converter --- p.96 / Chapter 7.7.1 --- Measurement Setup for the Phase Difference --- p.97 / Chapter 7.7.2 --- Phase Difference Measurement --- p.98 / Chapter 7.7.3 --- Discussion --- p.99 / Chapter Chapter8 --- Conclusion --- p.100 / Chapter Appendix A --- Characteristics of the Gilbert Quad Pair --- p.102 / Chapter A.1 --- Large-Signal Analysis --- p.102 / Chapter Appendix B --- Characteristics of the V-I Converter --- p.105 / Chapter B.1 --- Large-Signal Analysis --- p.105 / Bibliography --- p.108