Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisor: Anthony P. Ambler. Vita. Includes bibliographical references. Also available from UMI.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 100-102). Also available in electronic version.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 83-85). Also available in electronic version.

University of Macau / Faculty of Science and Technology / Department of Electrical and Computer Engineering

D.Ing. / This thesis initially reviews current empirical and probabilistic electrical load models available to distribution design engineers today to calculate voltage regulation levels in low voltage residential, commercial and light industrial consumer networks. Although both empirical and probabilistic techniques have extensively been used for residential consumers in recent years, it has been concluded that commercial and light industrial consumer loads have not been a focus area of probabilistic load study for purposes of low voltage feeder design. However, traditional empirical techniques, which include adjustments for diversity to accommodate non-coincidental electrical loading conditions, have generally been found to be applied using in-house design directives with only a few international publications attempting to address the problem. This work defines the light industrial group of consumers in accordance with its international Standard Industrial Classification (SIC) and presents case studies on a small group of three different types of light industrial sub-classes, It is proposed and proved that the electrical load models can satisfactorily be described as beta-distributed load current models at the instant of group or individual maximum power demand on typical characteristic 24-hour load cycles. Characteristic mean load profiles were obtained by recording repetitive daily loading of different sub-classes, ensuring adequate sample size at all times. Probabilistic modelling of light industrial loads using beta-distributed load current at maximum demand is a new innovation in the modelling of light industrial loads. This work is further -complemented by the development of a new probabilistic summation algorithm in spreadsheet format. This algorithm adds any selected number of characteristic load current profiles, adjusted for scale, power factor, and load current imbalance, and identifies the combined instant of group or system maximum demand. This spreadsheet also calculates the characteristic beta pdf parameters per phase describing the spread and profile of the combined system loading at maximum demand. These parameters are then conveniently used as input values to existing probabilistic voltage regulation algorithms to calculate voltage regulation in single-, bi- and three-phase low voltage distribution networks.

Chan Shek-Hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 94-97). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Table of Contents --- p.v / List of Figures --- p.ix / List of Tables --- p.xiii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Significance of the research --- p.2 / Chapter 1.3 --- Objectives --- p.3 / Chapter 1.4 --- Thesis outline --- p.4 / Chapter Chapter 2 --- Background theory --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Electrical properties of MOS transistors --- p.5 / Chapter 2.2.1 --- Strong inversion --- p.5 / Chapter 2.2.2 --- Weak inversion --- p.6 / Chapter 2.2.3 --- Moderate inversion --- p.8 / Chapter 2.2.4 --- The transistors biased in this work --- p.8 / Chapter 2.3 --- Rail-to-rail signals --- p.8 / Chapter 2.4 --- Rail-to-rail operational amplifier --- p.10 / Chapter 2.4.1 --- Rail-to-rail differential input pairs --- p.10 / Chapter 2.4.1.1 --- Principle --- p.10 / Chapter 2.4.1.2 --- Two stage operational amplifier --- p.13 / Chapter 2.4.2 --- Folded-cascode gain stage --- p.14 / Chapter 2.5 --- The nature of operational amplifier distortion --- p.16 / Chapter 2.5.1 --- The total harmonic distortion --- p.17 / Chapter Chapter 3 --- Constant transconductance rail-to-rail input stage --- p.20 / Chapter 3.1 --- Introduction --- p.20 / Chapter 3.2 --- Review of constant-gm input stage --- p.20 / Chapter 3.2.1 --- Rail-to-rail input stages with current-based gm control --- p.20 / Chapter 3.2.1.1 --- gm controlled by three-times current mirror --- p.21 / Chapter 3.2.1.2 --- gm controlled by square root current control --- p.23 / Chapter 3.2.1.3 --- gm controlled by using current switches only --- p.25 / Chapter 3.2.2 --- Rail-to-rail input stages with voltage-based gm control --- p.28 / Chapter 3.2.2.1 --- gm controlled by an ideal zener diode --- p.28 / Chapter 3.2.2.2 --- gm controlled by two diodes --- p.30 / Chapter 3.2.2.3 --- gm controlled by an electronic zener --- p.31 / Chapter 3.3 --- Conclusion --- p.32 / Chapter Chapter 4 --- Proposed constant transconductance rail-to-rail input stage --- p.34 / Chapter 4.1 --- Introduction --- p.34 / Chapter 4.2 --- Principle of the conventional input stage --- p.35 / Chapter 4.2.1 --- Translinear circuit --- p.35 / Chapter 4.3 --- Previous work --- p.36 / Chapter 4.3.1 --- Input bias circuit --- p.36 / Chapter 4.3.2 --- Weak inversion operation --- p.38 / Chapter 4.3.3 --- Power up problem --- p.43 / Chapter 4.4 --- Operational transconductance amplifier with proposed input biased stage --- p.47 / Chapter 4.4.1 --- Proposed input biased stage architecture --- p.47 / Chapter 4.4.2 --- Proposed input biased stage with 2 gm control circuits --- p.50 / Chapter 4.4.3 --- OTA with proposed input biased stage --- p.51 / Chapter Chapter 5 --- Simulation Results --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- DC bias simulation --- p.54 / Chapter 5.2.1 --- Total transconductance variation --- p.54 / Chapter 5.2.2 --- Power consumption --- p.56 / Chapter 5.3 --- AC simulation --- p.56 / Chapter 5.3.1 --- Open-loop gain --- p.57 / Chapter 5.3.2 --- Gain-bandwidth product --- p.59 / Chapter 5.3.3 --- Phase margin --- p.59 / Chapter 5.4 --- Transient simulation --- p.60 / Chapter 5.4.1 --- Voltage follower --- p.60 / Chapter 5.4.2 --- Total harmonic distortion --- p.62 / Chapter 5.4.3 --- Step response --- p.65 / Chapter 5.5 --- Conclusion --- p.67 / Chapter Chapter 6 --- Layout Consideration --- p.68 / Chapter 6.1 --- Introduction --- p.68 / Chapter 6.2 --- Substrate tap --- p.68 / Chapter 6.3 --- Input protection circuitry --- p.69 / Chapter 6.4 --- Die micrographs of the OTA --- p.71 / Chapter Chapter 7 --- Measurement Results --- p.74 / Chapter 7.1 --- Introduction --- p.74 / Chapter 7.2 --- DC bias measurement results --- p.74 / Chapter 7.2.1 --- Total transconductance variation --- p.74 / Chapter 7.2.2 --- Power consumption --- p.77 / Chapter 7.3 --- AC measurement results --- p.78 / Chapter 7.3.1 --- Open-loop gain --- p.78 / Chapter 7.3.2 --- Gain-bandwidth product --- p.81 / Chapter 7.3.3 --- Phase margin --- p.81 / Chapter 7.4 --- Transient measurement result --- p.82 / Chapter 7.4.1 --- Voltage follower --- p.82 / Chapter 7.4.2 --- Total harmonic distortion --- p.85 / Chapter 7.4.3 --- Step response --- p.87 / Chapter 7.5 --- Conclusion --- p.88 / Chapter Chapter 8 --- Conclusion --- p.90 / Chapter 8.1 --- Contribution --- p.90 / Chapter 8.2 --- Further development --- p.91 / Chapter Chapter 9 --- Appendix --- p.92 / Chapter Chapter 10 --- Bibliography --- p.94

Ho, Marco. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Sun, Lei. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Ching Lap Sze. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 69-71). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Shuttle Mask --- p.2 / Chapter 1.2 --- Voltage Island --- p.6 / Chapter 1.3 --- Structure of the Thesis --- p.8 / Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.1.1 --- Problem formulation --- p.10 / Chapter 2.2 --- Slicing Floorplan --- p.10 / Chapter 2.3 --- General Floorplan --- p.11 / Chapter 2.3.1 --- Conflict Graph Approaches --- p.11 / Chapter 2.3.2 --- Integer Linear Programming Approaches --- p.14 / Chapter 2.4 --- Grid Packing --- p.15 / Chapter 2.4.1 --- "(α,β,γ)-restricted Grid Approach" --- p.15 / Chapter 2.4.2 --- Branch and Bound Searching Approach --- p.17 / Chapter 3 --- Shuttle Mask Floorplanning --- p.18 / Chapter 3.1 --- Problem Description --- p.18 / Chapter 3.2 --- An Overview --- p.20 / Chapter 3.3 --- Modified α-Restricted Grid --- p.21 / Chapter 3.4 --- Branch and Bound Algorithm --- p.23 / Chapter 3.4.1 --- Feasibility Check --- p.25 / Chapter 3.5 --- Dicing Plan --- p.30 / Chapter 3.6 --- Experimental Result --- p.30 / Chapter 4 --- Literature Review on Voltage Island Partitioning --- p.36 / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Problem Definition --- p.36 / Chapter 4.2 --- Dynamic Programming --- p.38 / Chapter 4.2.1 --- Problem Definition --- p.38 / Chapter 4.2.2 --- Algorithm Overview --- p.38 / Chapter 4.2.3 --- Size Reduction --- p.39 / Chapter 4.2.4 --- Approximate Voltage-Partitioning --- p.40 / Chapter 4.3 --- Quad-tree Approach --- p.41 / Chapter 5 --- Voltage Island Partitioning --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Problem Formulation --- p.45 / Chapter 5.3 --- Methodology --- p.46 / Chapter 5.3.1 --- Coarsening and Graph Construction --- p.47 / Chapter 5.3.2 --- Tree Construction --- p.49 / Chapter 5.3.3 --- Optimal Tree Partitioning --- p.50 / Chapter 5.3.4 --- Tree Refinement --- p.52 / Chapter 5.3.5 --- Solution Legalization --- p.53 / Chapter 5.3.6 --- Time Complexity --- p.54 / Chapter 5.4 --- Direct Method --- p.55 / Chapter 5.4.1 --- Dual Grid-partitioning Problem (DGPP) --- p.56 / Chapter 5.4.2 --- Time Complexity --- p.58 / Chapter 5.5 --- Experimental Results --- p.59 / Chapter 6 --- Conclusion --- p.66 / Bibliography --- p.69

電源管理集成電路被廣泛應用於便攜式電子應用。在同一芯片需要不同的電源電壓水平。由於芯片尺寸，工作速度和所需功耗的要求，低壓差穩壓器（LDO）在快遞瞬態響應，低噪聲，以及高精度的電子產品中具有廣泛的應用。 / LDO的負載瞬間變化取決於功率金氧半場效電晶體的大小、偏置電流和誤差放大器的增益。檢測輸出電壓，並使用大電容和電阻通過電容耦合，增加偏置電流是一個簡單的方法來改善負載瞬間變化。然而，電阻電容佔據較大的芯片面積。 / 權衡功耗和芯片尺寸，本論文中提出用數字檢測電路取代用於瞬態耦合的大電容和電阻。所提出的電路是讓功率金氧半場效電晶體的栅極電容電流增加充電或放電，以提高LDO的負載瞬間響應速度。產生這種電流通過檢測內部的變化，並產生一個電壓脈衝控制迴轉電流，然後通過使用一組數字電路去改變充電或放電的電量。 / 擬議的設計已在UMC0.18微米 CMOS制程技術實現。LDO的輸入電壓為0.9伏至1.3伏和穩壓0.7伏。最大輸出電流為50豪安。經過測量，負載瞬間變化得到改善。負載瞬間的響應時間可以從75微秒（傳統）減少到75納秒。 / Power-management IC is widely used in portable electronic applications. Different supply voltage levels are required in the same chip. Due to the size, speed and power requirements, low-dropout regulator (LDO) is generally adopted for applications which need fast transient response, low noise and high accuracy. / Transient response of a LDO is limited by the size of power MOSFET, biasing current and gain of error amplifier. Detecting the output voltage and using large RC components for capacitive coupling to increase the biasing current is a straightforward method to improve the transient response. However, this requires a large chip size for the RC components. / By considering power consumption and size, digital detection circuit is proposed to replace the large capacitors and resistors used for transient coupling. The proposed circuit is to increase the charging or discharging current to the gate of the power MOSFET to increase the transient speed of LDO. This current is generated by detecting the internal changes and generating a voltage pulse to control the slewing current by using a set of digital circuit. / The proposed design has been realized in UMC 0.18μm CMOS technology. The input voltage of the LDO is 0.9 to 1.3V and the regulated voltage is 0.7V. The maximum output current is 50mA. From the measurement, the transient response is improved. The response time due to load transient changes can be reduced from 75s (conventional) to 75ns. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Kwong, Ka Yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract / Acknowledgments / Table of Content / List of Figures / List of Tables / Chapter Chapter 1 --- LDO regulator research background / Introduction / Chapter Section 1.1 --- Generic LDO regulator structure / Chapter Section 1.2 --- Principle of LDO regulator operation / Chapter Section 1.3 --- Specifications / Chapter References / Chapter Chapter 2 --- Review of state-of-the-art transient-improvement techniques for LDO regulators / Introduction / Chapter Section 2.1 --- Slew rate improvement at power transistor gate / Chapter Section 2.2 --- Frequency compensation / Chapter Section 2.3 --- Short summary / References / Chapter Chapter 3 --- A proposed output-capacitorless LDO regulator with digital voltage spike detection / Chapter Introduction / Chapter Section 3.1 --- LDO regulator core structure / Chapter Section 3.2 --- Digital switches based LDO regulator / Chapter Section 3.3 --- LDO regulator with proposed digital voltage spike detection circuit / Chapter Section 3.4 --- Simulation result / Chapter Section 3.5 --- Short summary / References / Chapter Chapter 4 --- Measurement results / Introduction / Chapter Chapter 5 --- Conclusion and Future Work