Thesis (M.S.)--Wisconsin. / Includes bibliographical references (leaves [87-89]).

by Cheng Wang Chi. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 108-111). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.iii / Acknowledgments --- p.v / Contents --- p.vii / List of Tables --- p.xiii / List of Figures --- p.xiv / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Technical Challenges of CMOS RF Design --- p.2 / Chapter 1.3 --- General Background --- p.2 / Chapter 1.3.1 --- Bipolar and CMOS Mixers --- p.4 / Chapter 1.4 --- Research Goal --- p.4 / Chapter 1.5 --- Thesis Outline --- p.5 / Chapter Chapter2 --- RF Fundamentals --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Frequency Translation --- p.6 / Chapter 2.3 --- Conversion Gain --- p.8 / Chapter 2.4 --- Linearity --- p.8 / Chapter 2.4.1 --- 1-dB Compression Point --- p.11 / Chapter 2.4.2 --- Third Intercept Point (IP3) --- p.11 / Chapter 2.5 --- Dynamic Range (DR) --- p.13 / Chapter 2.5.1 --- Spurious-Free Dynamic Range (SFDR) --- p.13 / Chapter 2.5.2 --- Blocking Dynamic Range (BDR) --- p.14 / Chapter 2.6 --- Blocking and Desensitization --- p.15 / Chapter 2.7 --- Port-to-Port Isolation --- p.15 / Chapter 2.8 --- Single-Balanced and Double-Balanced Mixers --- p.16 / Chapter 2.9 --- Noise --- p.16 / Chapter 2.9.1 --- Noise in the Local Oscillator --- p.17 / Chapter 2.9.2 --- Noise Figure --- p.18 / Chapter Chapter3 --- Downconversion Mixer --- p.19 / Chapter 3.1 --- Introduction --- p.19 / Chapter 3.2 --- Review of Mixer Topology --- p.19 / Chapter 3.2.1 --- Square-Law Mixer --- p.20 / Chapter 3.2.2 --- CMOS Gilbert Cell --- p.21 / Chapter 3.2.3 --- Potentiometric Mixer --- p.22 / Chapter 3.2.4 --- Subsampling Mixer --- p.23 / Chapter Chapter4 --- Proposed Downconversion Mixer --- p.24 / Chapter 4.1 --- Analysis of Proposal Mixer --- p.24 / Chapter 4.2 --- Current Folded Mirror Mixer --- p.24 / Chapter 4.2.1 --- Operating Principle --- p.25 / Chapter 4.2.2 --- Large Signal Analysis --- p.26 / Chapter 4.2.3 --- Small Signal Analysis --- p.29 / Chapter 4.3 --- Current Mode Mixer --- p.32 / Chapter 4.3.1 --- Operating Principle --- p.33 / Chapter 4.3.2 --- Large Signal Analysis --- p.33 / Chapter 4.3.3 --- Small Signal Analysis --- p.34 / Chapter 4.3.4 --- V-I Converter --- p.36 / Chapter 4.3.4.1 --- Equation Analysis --- p.37 / Chapter 4.4 --- Second Order Effects --- p.38 / Chapter 4.4.1 --- Device Mismatch --- p.38 / Chapter 4.4.2 --- Body Effect --- p.39 / Chapter 4.5 --- Single-ended to Differential-ended converter --- p.39 / Chapter 4.6 --- Output Buffer Stage --- p.40 / Chapter 4.7 --- Noise Theory --- p.41 / Chapter 4.7.1 --- SSB and DSB Noise Figure --- p.42 / Chapter 4.7.2 --- Noise Figure --- p.43 / Chapter Chapter5 --- Simulation Results --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Current Folded Mirror Mixer --- p.44 / Chapter 5.2.1 --- Conversion Gain --- p.45 / Chapter 5.2.2 --- Linearity --- p.46 / Chapter 5.2.2.1 --- 1dB Compression Point and IIP3 --- p.49 / Chapter 5.2.3 --- Output Buffer Stage --- p.49 / Chapter 5.3 --- Current Mode Mixer --- p.51 / Chapter 5.3.1 --- Conversion Gain --- p.51 / Chapter 5.3.2 --- Linearity --- p.52 / Chapter 5.3.2.1 --- 1-dB Compression Point and IIP3 --- p.52 / Chapter 5.3.3 --- Output Buffer Stage --- p.53 / Chapter 5.3.4 --- V-I Converter --- p.54 / Chapter 5.4 --- Single-ended to Differential-ended Converter --- p.55 / Chapter Chapter6 --- Layout Consideration --- p.57 / Chapter 6.1 --- Introduction --- p.57 / Chapter 6.2 --- CMOS transistor Layout --- p.57 / Chapter 6.3 --- Resistor Layout --- p.59 / Chapter 6.4 --- Capacitor Layout --- p.60 / Chapter 6.5 --- Substrate Tap --- p.62 / Chapter 6.6 --- Pad Layout --- p.63 / Chapter 6.7 --- Analog Cell Layout --- p.64 / Chapter Chapter7 --- Measurements --- p.65 / Chapter 7.1 --- Introduction --- p.65 / Chapter 7.2 --- Downconversion mixer --- p.66 / Chapter 7.3 --- PCB Layout --- p.66 / Chapter 7.4 --- Test Setups --- p.68 / Chapter 7.4.1 --- Measurement Setup for S-Parameter --- p.68 / Chapter 7.4.2 --- Measurement Setup for 1-dB Compression Point and IIP3 --- p.70 / Chapter 7.5 --- Measurement Result of the Current Folded Mirror Mixer --- p.72 / Chapter 7.5.1 --- S-Parameter Measurement --- p.75 / Chapter 7.5.2 --- Conversion Gain and the Effect of the IF Variation --- p.77 / Chapter 7.5.3 --- 1-dB Compression Point --- p.78 / Chapter 7.5.4 --- IIP3 --- p.79 / Chapter 7.5.5 --- LO Power Effect to the Mixer --- p.81 / Chapter 7.5.6 --- Performance Summaries of the Current Folded Mirror Mixer --- p.82 / Chapter 7.5.7 --- Discussion --- p.83 / Chapter 7.6 --- Measurement Result of the Current Mode Mixer --- p.84 / Chapter 7.6.1 --- S-Parameter Measurement --- p.87 / Chapter 7.6.2 --- Conversion Gain and the Effect of the IF Variation --- p.89 / Chapter 7.6.3 --- 1-dB Compression Point --- p.90 / Chapter 7.6.4 --- IIP3 --- p.91 / Chapter 7.6.5 --- LO Power Effect to the Mixer --- p.93 / Chapter 7.6.6 --- Performance Summaries of the Current Mode Mixer --- p.94 / Chapter 7.6.7 --- Discussion --- p.95 / Chapter 7.7 --- Measurement Result of the Single-ended to Differential-ended converter --- p.96 / Chapter 7.7.1 --- Measurement Setup for the Phase Difference --- p.97 / Chapter 7.7.2 --- Phase Difference Measurement --- p.98 / Chapter 7.7.3 --- Discussion --- p.99 / Chapter Chapter8 --- Conclusion --- p.100 / Chapter Appendix A --- Characteristics of the Gilbert Quad Pair --- p.102 / Chapter A.1 --- Large-Signal Analysis --- p.102 / Chapter Appendix B --- Characteristics of the V-I Converter --- p.105 / Chapter B.1 --- Large-Signal Analysis --- p.105 / Bibliography --- p.108

Thesis (Ph. D.)--Ohio State University, 2007. / Title from first page of PDF file. Includes bibliographical references (p. 104-107).

For the first method, a novel linearization scheme for CMOS double-balanced mixer based on the use of multi-bias dual-gate transistors is presented. In this technique, two intermodulation distortion components with proper phase relationship, generated by devices operating at different bias conditions, are added together to cancel each other for the improvement of mixer's linearity. The measured performance of a fabricated CMOS mixer operating at RF frequency of 2.45GHz and LO frequency of 2.35GHz is demonstrated. Over 35dB of IMD reduction is achieved by the proposed method under optimal biasing condition. / In the second design, a novel linearization scheme for cascode amplifier based upon capacitive feedback is presented. This method involves the optimal design of the feedback network for IMD reduction. By using Volterra series analysis, expression for IMD products is derived and the corresponding circuit parameters for optimized linearity are obtained. For experimental verification, CMOS cascode amplifiers are designed and fabricated to operate at 2.45GHz with supply voltage of 2V. By measurement, IIP3 is improved of almost 7dB by using the proposed feedback technique. The performance dependency of the fabricated amplifiers under different bias conditions is also examined. The results indicate that the proposed technique can offer low sensitivity to the variation of process parameters. / Linearity is one of the major requirements in modern communication systems due to the limited channel spacing. In the past years, various linearization schemes have been studied extensively for RF circuit design such as low-noise amplifiers and power amplifiers. These techniques offer IMD reduction at the expense of circuit complexity. In the last decade, much effort has been devoted to the development of single-chip RF transceiver using sub-micron CMOS technology. This thesis presents three simple and effective linearization techniques for CMOS mixer and amplifier design. They are experimentally verified by circuit fabrication based on 0.35mum CMOS process. / The last approach combines the advantages of source degeneration and the capacitive feedback for cascode amplifier linearization. Experiments are performed on CMOS amplifiers operating at 2.45GHz, and more than 11dB of IIP3 enhancement is observed. / Au Yeung, Chung Fai. / "August 2007." / Adviser: Chang Kwok Keung. / Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1189. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 153-161). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.

Au-Yeung Chung-Fai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 85-91). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Contents --- p.iv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Basic Theory of Mixer --- p.6 / Chapter 2.1 --- Definition of mixer's electrical parameters --- p.8 / Chapter 2.2.1 --- Conversion gain --- p.8 / Chapter 2.2.2 --- Port-to-port isolation --- p.8 / Chapter 2.2.3 --- Noise figure --- p.9 / Chapter 2.2.4 --- 1-dB compression point (P1dB) --- p.11 / Chapter 2.2.5 --- 2nd order intercept point (IP2) --- p.11 / Chapter 2.2.6 --- 3rd order intercept point (IP3) --- p.12 / Chapter 2.2.7 --- Blocking dynamic range (BDR) --- p.12 / Chapter 2.2.8 --- Spurious free dynamic range (SFDR) --- p.12 / Chapter 2.2 --- Review of mixer architectures --- p.13 / Chapter 2.2.1 --- Diode mixer --- p.13 / Chapter 2.2.2 --- Dual-gate mxer --- p.14 / Chapter 2.2.3 --- Singly balanced mixer --- p.15 / Chapter 2.2.4 --- Doubly balanced dual-gate mixer --- p.16 / Chapter 2.2.5 --- Gilbert cell mixer --- p.18 / Chapter Chapter 3 --- CMOS Doubly Balanced Dual-Gate Mixer Design --- p.20 / Chapter 3.1 --- Design and Analysis --- p.20 / Chapter 3.1.1 --- Principle of operation --- p.20 / Chapter 3.1.2 --- Doubly balanced dual-gate mixer --- p.23 / Chapter 3.1.3 --- Common source output buffer --- p.25 / Chapter 3.1.4 --- Design example and simulation results --- p.26 / Chapter 3.2 --- IC Layout --- p.29 / Chapter 3.2.1 --- Multi-fingers transistor --- p.29 / Chapter 3.2.2 --- Matched transistor --- p.31 / Chapter 3.2.3 --- Match resistor --- p.32 / Chapter 3.2.4 --- Layout of CMOS doubly balanced dual-gate mixer --- p.33 / Chapter Chapter 4 --- Review of Mixer Linearization Techniques --- p.34 / Chapter 4.1 --- Source degeneration --- p.34 / Chapter 4.2 --- Feed-forward system --- p.36 / Chapter 4.3 --- Predistortion --- p.38 / Chapter 4.4 --- Difference-frequency (low-frequency) injection technique --- p.41 / Chapter Chapter 5 --- Mixer Linearization 一 Low Frequency Signal Injection --- p.44 / Chapter 5.1 --- Mixer's linearity --- p.44 / Chapter 5.2 --- Low-frequency signal injection method --- p.46 / Chapter 5.2.1 --- Single-injection scheme --- p.49 / Chapter 5.2.2 --- Dual-injection scheme --- p.50 / Chapter 5.2.3 --- Effect of gain error --- p.51 / Chapter 5.2.4 --- Bandwidth lim itation --- p.52 / Chapter Chapter 6 --- Experiments and Results --- p.55 / Chapter 6.1 --- CMOS doubly balanced dual-gate mixer --- p.55 / Chapter 6.1.1 --- Conversion gain --- p.56 / Chapter 6.1.2 --- Port-to-port isolation --- p.57 / Chapter 6.1.3 --- No ise figure --- p.60 / Chapter 6.1.4 --- 1-dB compression point --- p.61 / Chapter 6.1.5 --- 3rd order intercept point --- p.62 / Chapter 6.2 --- Low-frequency signal injection method --- p.63 / Chapter 6.2.1 --- Measurement result: single-injection scheme --- p.64 / Chapter 6.2.2 --- Measurement result: dual-injection scheme --- p.66 / Chapter Chapter 7 --- Conclusions and Recommendations for Future Work --- p.68 / Chapter 7.1 --- Conclusions --- p.68 / Chapter 7.2 --- Recommendations for future work --- p.69 / Appendix --- p.70 / Chapter A1 --- CMOS technology --- p.70 / Chapter A1.1 --- MOSFET structure --- p.70 / Chapter A1.2 --- CMOS n-well process --- p.71 / Chapter A1.3 --- MOSFET device modeling --- p.74 / Chapter A1.4 --- Channel length modulation --- p.78 / Chapter A1.5 --- Body effect --- p.78 / Chapter A2 --- Mixer's nonlinearity analysis --- p.79 / Chapter A2.1 --- First-order effect --- p.79 / Chapter A2.2 --- Second-order effect --- p.80 / Chapter A2.3 --- Third-order effect --- p.81 / Chapter A2.4 --- Nonlinear IF spectrum --- p.82 / Chapter A3 --- Artificial IMD3 produced by low-frequency signal injection --- p.83 / Author's Publication List --- p.85 / References --- p.86

We present a new circuit design for adaptive offset cancellation in a fully differential 2.4 GHz CMOS direct conversion mixer. Our circuit structure is a modification of a Gilbert cell mixer in which offsets are cancelled by injecting cancellation currents into the legs of the mixer by dynamically varying the bias on the active loads. We present analysis and simulation results of our mixer with offsets present. Offsets create non-linearities in any circuit by differentially shifting the small-signal bias point of a matched pair; forcing once symmetrical transistors to operate in different bias regions and create second order distortion. We focus our design to minimize second order distortion while simultaneously canceling the large offsets found in direct conversion receivers. Simulation results for the mixer canceling a wide range of offsets are included. Our mixer has a gain of 6.4dB, an IIP3 of 17dBm and a noise figure of 17dB as simulated in a .5��m HP Mosis CMOS process. / Graduation date: 2002

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 158-164).