Invasive and non-invasive methods of BTI monitoring and wearout preemption have been proposed. We propose a novel, simple to use, test structure for NBTI /PBTI monitoring. The proposed structure has an AC and a DC stress mode. Although during stress mode, both PMOS and NMOS devices are stressed, the proposed structure isolates the PBTI and NBTI degradation during test mode. A methodology of converting any data-path into ring oscillator (DPRO) is also presented. To avoid the performance overhead of attaching monitoring circuitry to functional block, a non-invasive scheme for BTI monitoring is presented for sleep transistor based logic families. Since, BTI is a critical issue for memories, a scheme for BTI monitoring of 6T SRAM cell based memories is also presented. We make use of the concept of a DPRO and show how a memory system can be made to oscillate in test mode. The frequency of oscillation is a function of the devices in the cell. After validation of the proposed schemes using extensive simulations, we have also validated the results on silicon. We also introduce the concept of wearout mitigation at the compiler level. Using an example of a register file, we present a preemptive method of wearout mitigation using a compiler directed scheme.
| Identifer | oai:union.ndltd.org:GATECH/oai:smartech.gatech.edu:1853/52227 |
| Date | 27 August 2014 |
| Creators | Ahmed, Fahad |
| Contributors | Milor, Linda S. |
| Publisher | Georgia Institute of Technology |
| Source Sets | Georgia Tech Electronic Thesis and Dissertation Archive |
| Detected Language | English |
| Type | Dissertation |
| Format | application/pdf |
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