Invasive and non-invasive methods of BTI monitoring and wearout preemption have been proposed. We propose a novel, simple to use, test structure for NBTI /PBTI monitoring. The proposed structure has an AC and a DC stress mode. Although during stress mode, both PMOS and NMOS devices are stressed, the proposed structure isolates the PBTI and NBTI degradation during test mode. A methodology of converting any data-path into ring oscillator (DPRO) is also presented. To avoid the performance overhead of attaching monitoring circuitry to functional block, a non-invasive scheme for BTI monitoring is presented for sleep transistor based logic families. Since, BTI is a critical issue for memories, a scheme for BTI monitoring of 6T SRAM cell based memories is also presented. We make use of the concept of a DPRO and show how a memory system can be made to oscillate in test mode. The frequency of oscillation is a function of the devices in the cell. After validation of the proposed schemes using extensive simulations, we have also validated the results on silicon. We also introduce the concept of wearout mitigation at the compiler level. Using an example of a register file, we present a preemptive method of wearout mitigation using a compiler directed scheme.

Shrinking transistor sizes have introduced new challenges and opportunities for system-on-chip (SoC) design and reliability. Smaller transistors are more susceptible to early lifetime failure and electronic wear-out, greatly reducing their reliable lifetimes. However, smaller transistors will also allow SoC to contain hundreds of processing cores and other infrastructure components with the potential for increased reliability through massive structural redundancy. Concurrent online testing (COLT) can provide sufficient reliability and availability to systems with this redundancy. COLT manages the process of testing a subset of processing cores while the rest of the system remains operational. This can be considered a temporary, graceful degradation of system performance that increases reliability while maintaining availability. In this dissertation, techniques to assist COLT are proposed and analyzed. The techniques described in this dissertation focus on two major aspects of COLT feasibility: recovery time and test delivery costs. To reduce the time between failure and recovery, and thereby increase system availability, an anomaly-based test triggering unit (ATTU) is proposed to initiate COLT when anomalous network behavior is detected. Previous COLT techniques have relied on initiating tests periodically. However, determining the testing period is based on a device's mean time between failures (MTBF), and calculating MTBF is exceedingly difficult and imprecise. To address the test delivery costs associated with COLT, a distributed test vector storage (DTVS) technique is proposed to eliminate the dependency of test delivery costs on core location. Previous COLT techniques have relied on a single location to store test vectors, and it has been demonstrated that centralized storage of tests scales poorly as the number of cores per SoC grows. Assuming that the SoC organizes its processing cores with a regular topology, DTVS uses an interleaving technique to optimally distribute the test vectors across the entire chip. DTVS is analyzed both empirically and analytically, and a testing protocol using DTVS is described. COLT is only feasible if the applications running concurrently are largely unaffected. The effect of COLT on application execution time is also measured in this dissertation, and an application-aware COLT protocol is proposed and analyzed. Application interference is greatly reduced through this technique.

Adhesive bonding is one of the most attractive joining techniques for any structural application, including high profile examples in the aerospace, automotive, marine construction and electrical industries. Advantages of adhesive bonding include; superior fatigue performance, better stress distribution and higher stiffness than conventional joining techniques. When the design of bonded joints is considered, fatigue is of critical importance in most structural applications. There are two main issues that are of importance; a) in-service damage characterisation during fatigue loading and, b) lifetime prediction under both constant and variable amplitude fatigue loading. If fatigue damage characterisation is considered, there has been some work to characterise damage in-situ using the backface strain (BFS) measurement technique, however, there has been little investigation of the effects of different types of fatigue behaviour under different types of geometry and loading. Regarding fatigue lifetime prediction of bonded joints, most of the work in the literature is concentrated with constant amplitude fatigue, rather than variable amplitude fatigue. Fatigue design of a bonded structure based on constant amplitude fatigue, when the actual loading on the structure is of the variable amplitude fatigue, can result in erroneous lifetime prediction. This is because of load interaction effects caused by changes in load ratio, mean load etc., which can decrease the fatigue life considerably. Therefore, the project aims to a) provide a comprehensive study of the use of BFS measurements to characterise fatigue damage, b) develop novel techniques for predicting lifetime under constant amplitude fatigue and c) provide an insight into various types of load interaction effects. In this project, single lap joints (SLJ) and compound double cantilever beam geometries were used. Compound double cantilever beams were used mainly to determine the critical strain energy release rate and to obtain the relationship between strain energy release rate and fatigue crack growth rate. The fatigue life of SLJs was found to be dominated by crack initiation at lower fatigue loads. At higher fatigue loads, fatigue life was found to consist of three phases; initiation, stable crack propagation and fast crack growth. Using these results, a novel damage progression model was developed, which can be used to predict the remaining life of a bonded structure. A non-linear strength wearout model (NLSWM) was also proposed, based on strength wearout experiments, where a normalised strength wearout curve was found to be independent of the fatigue load applied. In this model, an empirical parameter determined from a small number of experiments, can be used to determine the residual strength and remaining life of a bonded structure. A fracture mechanics approach based on the Paris law was also used to predict the fatigue lifetime under constant amplitude fatigue. This latter method was found to under-predict the fatigue life, especially at lower fatigue loads, which was attributed to the absence of a crack initiation phase in the fracture mechanics based approach. A damage mechanics based approach, in which a damage evolution law was proposed based on plastic strain, was found to predict the fatigue life well at both lower and higher fatigue loads. This model was able to predict both initiation and propagation phases. Based on the same model, a unified fatigue methodology (UFM) was proposed, which can be used to not only predict the fatigue lifetime, but also various other fatigue parameters such as BFS, strength wearout and stiffness wearout. The final part of the project investigated variable amplitude fatigue. In this case, fatigue lifetime was found to decrease, owing to damage and crack growth acceleration in various types of variable amplitude fatigue loading spectra. A number of different strength wearout approaches were proposed to predict fatigue lifetime under variable amplitude fatigue loading. The NLSWM, where no interaction effects were considered was found to over-predict the fatigue life, especially at lower fatigue loads. However, approaches such as the modified cycle mix and normalised cycle mix approaches were found to predict the fatigue life well at all loads and for all types of variable amplitude fatigue spectra. Progressive damage models were also applied to predict fatigue lifetime under variable amplitude fatigue loading. In this case a fracture mechanics based approach was found to under-predict the fatigue life for all types of spectra at lower loads, which was established to the absence of a crack initiation phase in this method. Whereas, a damage mechanics based approach was found to over-predict the fatigue lifetime for all the types of variable amplitude fatigue spectra, however the over- prediction remained mostly within the scatter of the experimental fatigue life data. It was concluded that, the damage mechanics based approach has potential for further modification and should be tested on different types of geometry and spectra.

Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.

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