Microelectronic devices and systems have been extensively utilized in a variety of radiation
environments, ranging from the low-earth orbit to the ground level. A high-energy particle from
such an environment may cause voltage/current transients, thereby inducing Single Event Effect
(SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975,
this community has made tremendous progress in investigating the mechanisms of SEE and
exploring radiation tolerant techniques. However, as the IC technology advances, the existing
hardening techniques have been rendered less effective because of the reduced spacing and
charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has
identified radiation-induced soft errors as the major threat to the reliable operation of electronic
systems in the future. In digital systems, hardening techniques of their core components, such as
latches, logic, and clock network, need to be addressed.
Two single event tolerant latch designs taking advantage of feedback transistors are
presented and evaluated in both single event resilience and overhead. These feedback transistors
are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in
a larger feedback delay and higher single event tolerance. On the other hand, these extra
transistors are turned ON when the cell is in the write mode. As a result, no significant write
delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section
when compared to the reference cells.
Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The
worst case occurs when the output is evaluated logic high, where the pull-up networks are turned
OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail.
A capacitor added to the feedback path increases the node capacitance of the output and the
feedback delay, thereby increasing the single event critical charge. Another differential structure
that has two differential inputs and outputs eliminates single event upset issues at the expense of
an increased number of transistors.
Clock networks in advanced technology nodes may cause significant errors in an IC as the
devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme
in a digital system. It was fabricated in a 28nm technology and evaluated through the use of
heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was
demonstrated during these tests.
In addition to mitigating single event issues by using hardened designs, built-in current
sensors can be used to detect single event induced currents in the n-well and, if implemented,
subsequently execute fault correction actions. These sensors were simulated and fabricated in a
28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of
this sensor design. This manifests itself as an alternative to existing hardening techniques.
In conclusion, this work investigates single event effects in digital systems, especially those
in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock,
and current sensor designs have been presented and evaluated. Through the use of these designs,
the single event tolerance of a digital system can be achieved at the expense of varying overhead
in terms of area, power, and delay.
| Identifer | oai:union.ndltd.org:USASK/oai:ecommons.usask.ca:10388/ETD-2015-08-2101 |
| Date | 2015 August 1900 |
| Contributors | Chen, Li |
| Source Sets | University of Saskatchewan Library |
| Language | English |
| Detected Language | English |
| Type | text, thesis |
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