Networks-on-Chip (NoCs) are a general purpose, scalable replacement for shared
medium wired interconnects offering many practical applications in industry. Dynamic
Voltage Frequency Scaling (DVFS) is a technique whereby a chip?s voltage-frequency
levels are varied at run time, often used to conserve dynamic power. Various DVFSbased
NoC optimization techniques have been proposed. However, due to the resources
required to validate architectural decisions through prototyping, few are implemented.
As a result, designers are faced with a lack of insight into potential power savings or
performance gains at early architecture stages.
This thesis proposes a DVFS aware NoC simulator with support for per node
power-frequency modeling to allow fine-tuning of such optimization techniques early on
in the design cycle. The proposed simulator also provides a framework for
benchmarking various candidate strategies to allow selective prototyping and
optimization.
As part of the research, DVFS extensions were built for an existing NoC
performance simulator and released for public use. This thesis presents some of the preliminary results from our simulator that show the average power consumed per node
for all the benchmarks in SPLASH 2 benchmark suite [74] to be quite similar to each
other. This thesis also serves as a technical manual for the simulator extensions.
Important links for downloading and using the simulator are provided at the end of this
document in Appendix C.
| Identifer | oai:union.ndltd.org:tamu.edu/oai:repository.tamu.edu:1969.1/ETD-TAMU-2010-05-7798 |
| Date | 2010 May 1900 |
| Creators | Prabhu, Subodh |
| Contributors | Hu, Jiang, Gratz, Paul V. |
| Source Sets | Texas A and M University |
| Language | English |
| Detected Language | English |
| Type | Book, Thesis, Electronic Thesis, text |
| Format | application/pdf |
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