A reliable scheme to reuse IP (Intellectual Property) cores became an important issue to accelerate the development of embedded systems. Unfortunately the diverse characteristic of embedded systems which deep the difficulty of IP reuse. This thesis proposed the OCP-AHB bus interface architecture by designing a standard and general interface. The IP cores with OCP interface can plug-an-play in bus quickly. It solve the environment problems of the diverse embedded systems and the compatibility issues between IP cores and on-chip interconnections, so the IP reuse ability are raised and the IP designer can focus only on their designs. There are four different versions of OCP-AHB bus interface according to the input and output interface designs. The porposed OCP-AHB bus interface has the better performance and small hardware area when IP transfer data each others through the bus. The result show the proposed architecture can reduce the system integration and verification time and the proposed architecture are actually use in three-dimensional graphics (3D Graphics) processor application.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0818111-151445 |
| Date | 18 August 2011 |
| Creators | Kuo, Kuan-Fu |
| Contributors | none, In-Jer Huang, none, none |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0818111-151445 |
| Rights | user_define, Copyright information available at source archive |
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