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Logic Synthesis of High-Performance Combinational Circuits Based on Pass-Transistor Cell Library

This thesis proposes a new variable-order prediction method to predict the Shannon expansion order during the BDD tree generator. Combining this method with the original minimum width method, we can generator a better BDD tree to be used in our pass-transistor logic synthesizer. Also we propose two partitioning methods to reduce the length of the critical paths. The first method can effectively reduce the critical path delay at the cost of much higher area cost. The second method explores the common factors in the Boolean functions to reduce the critical path delay with reasonably increased area cost. Furthermore, we discuss the methods of inserting regenerating inverters/buffers along the path in BDD tree by selecting inverter cells and MUX cells of proper driving strength to optimize the area/cost/power performance. Finally, the automatic layout generation is considered to produce the physical layout more efficiently compared with that using commericial automatic place-and-route tools.

Identiferoai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0902103-215924
Date02 September 2003
CreatorsWen, Chia-Sheng
ContributorsChung-Ho Chen, Shiann-Rong Kuang, Shen-Fu Hsiao
PublisherNSYSU
Source SetsNSYSU Electronic Thesis and Dissertation Archive
LanguageCholon
Detected LanguageEnglish
Typetext
Formatapplication/pdf
Sourcehttp://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0902103-215924
Rightswithheld, Copyright information available at source archive

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