abstract: Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include high speed and endurance, extreme scalability, ease of fabrication, ultra low power operation, and perhaps most importantly ease of integration with the CMOS back end of line (BEOL) process flow. One area where detailed study is lacking is the reliability of PMC devices. In previous reliability work, the low and high resistance states were monitored for periods of hours to days without any applied voltage and the results were extrapolated to several years (>10) but little has been done to analyze the low resistance state under stress. With or without stress, the low resistance state appears to be highly stable but a gradual increase in resistance with time, less than one order of magnitude after ten years when extrapolated, has been observed. It is important to understand the physics behind this resistance rise mechanism to comprehend the reliability issues associated with the low resistance state. This is also related to the erase process in PMC cells where the transition from the ON to OFF state occurs under a negative voltage. Hence it is important to investigate this erase process in PMC cells under different conditions and to model it. Analyzing the programming and the erase operations separately is important for any memory technology but its ability to cycle efficiently (reliably) at low voltages and for more than 1E4 cycles (without affecting the cells performance) is more critical. Future memory technologies must operate with the low power supply voltages (<1V) required for small geometry nodes. Low voltage programming of PMC memory devices has previously been demonstrated using slow voltage sweeps and small numbers of fast pulses. In this work PMC memory cells were cycled at low voltages using symmetric pulses with different load resistances and the distribution of the ON and OFF resistances was analyzed. The effect of the program current used during the program-erase cycling on the resulting resistance distributions is also investigated. Finally the variation found in the behavior of similar resistance ON states in PMC cells was analyzed more in detail and measures to reduce this variation were looked into. It was found that slow low current programming helped reducing the variation in erase times of similar resistance ON states in PMC cells. This scheme was also used as a pre-conditioning technique and the improvements in subsequent cycling behavior were compared. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011
| Identifer | oai:union.ndltd.org:asu.edu/item:8848 |
| Date | January 2011 |
| Contributors | Kamalanathan, Deepak (Author), Kozicki, Dr. Michael (Advisor), Schroder, Dr. Dieter (Committee member), Goryll, Dr. Michael (Committee member), Alford, Dr. Terry (Committee member), Arizona State University (Publisher) |
| Source Sets | Arizona State University |
| Language | English |
| Detected Language | English |
| Type | Doctoral Dissertation |
| Format | 140 pages |
| Rights | http://rightsstatements.org/vocab/InC/1.0/, All Rights Reserved |
Page generated in 0.0016 seconds