Physical Unclonable Functions are a unique class of circuits that leverage the inherentvariations in manufacturing process to create unique,unclonableIDs and secret keys.The distinguishing feature of PUFs is that even an untrusted foundry cannot create a copy of the circuit as it is impossible to control the manufacturing process variations.PUFs can operate reliably in presence of voltage and temperature variations. In thisthesis, weexplorethe security offered by PUFs and tradeoffs between different metrics such as uniqueness, reliability and energy consumption.Benefits of sub-threshold PUF operation and the use of delay based Arbiter PUFs and ring oscillator PUFs in low power applications is evaluated.
As we scale into lower technology nodes, there exists sufficient inter chip variation that enables each IC to be identified securely.The impact of scaling on the identification capabilities of a PUF and its reliability has been demonstrated in this work by analyzing the behavior of an Arbiter PUF in 45nm, 32nm and 22nm technology nodes. Further,the Arbiter PUF design has been implemented on a test-chip and fabricated using 45nm industry models andresults from post silicon validation are presented.
Finally, we investigate a new class of PUF circuits in this work, that provide better security against machine learning based software modeling attacks. The strong identification capabilities and sufficiently high reliability offered by these PUF circuits make them promising candidates for future applications requiring securehardware cryptographic primitives.
| Identifer | oai:union.ndltd.org:UMASS/oai:scholarworks.umass.edu:theses-1867 |
| Date | 01 January 2012 |
| Creators | Srivathsa, Sudheendra |
| Publisher | ScholarWorks@UMass Amherst |
| Source Sets | University of Massachusetts, Amherst |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Masters Theses 1911 - February 2014 |
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