Modern Printed Circuit Boards (PCB) contain sophisticated and valuable electronic components, and this makes them a prime target for counterfeiting. In this thesis, we consider a method to test if a PCB is genuine. One high-level solution is to use a secret identifier of the board, together with a cryptographic authentication protocol. We describe a mechanism that authenticates all major components of PCB as part of attesting the PCB. Our authentication protocol constructs the fingerprint of PCB by extracting hardware fingerprint from the components on PCB and cryptographically combining the fingerprints. Fingerprints from each component on PCB are developed using Physical Unclonable Functions (PUF). In this thesis, we present a PUF based authentication protocol for remote integrity checking using multiple PUF component level identifiers. We address the design on 3 different abstraction levels. 1)Hardware Level, 2)Hardware Integration level, 3)Protocol level. On the hardware level, we propose an approach to develop PUF from flash memory component on the device. At the hardware Integration level, we discuss a hardware solution for implementing a trustworthy PUF based authentication. We present a prototype of the PUF based authentication protocol on an FPGA board via network sockets. / Master of Science

Silicon physical unclonable functions (PUFs) are security primitives relying on the intrinsic randomness of IC manufacturing. Strong PUFs have a very large input-output space which is essential for secure authentication. Several proposed strong PUFs use timing races to produce a rich set of responses. However, these PUFs are vulnerable to machine-learning attacks due to linear separability of the output function resulting from the additive nature of timing delay along timing paths. We introduce a novel strong silicon PUF based on the exponential current-voltage behavior in subthreshold region of FET operation. This behaviour injects strong nonlinearity into the response of the PUF. The PUF, which we term subthreshold current array (SCA) PUF, is implemented as a two-dimensional n x k transistor array with all devices subject to stochastic variability operating in subthreshold region. Our PUF is fundamentally different from earlier attempts to inject nonlinearity via digital control techniques like XORing the outputs of PUF and using feedforward structures, which could also be used with SCA-PUF. Voltages produced by nominally identical arrays are compared to produce a random binary response. SCA-PUF shows excellent security properties. The average inter-class Hamming distance, a measure of uniqueness, is 50.3%. The average intra-class Hamming distance, a measure of response stability, is 0.6%. Crucially, we demonstrate that the introduced PUF is much less vulnerable to modeling attacks. Using a machine-learning technique of support-vector machine with radial basis function kernel for optimum nonlinear learnability, we observe that the information leakage (rate of error reduction with learning) is much lower than for delay-based PUFs. Specifically, over a wide range of the number of observed challenge-response pairs, the error rate is 3-35x higher than for earlier designs. / text

Additive Manufacturing (AM) is a unique method of fabrication that, in contrast to traditional manufacturing methods, builds objects layer by layer. The ability of AM (when partnered with 3D scanning) to clone physical objects has raised concerns in the area of intellectual property (IP). To address this issue, the goal of this dissertation is to characterize and model a method to incorporate unique security features within AM builds. By adding optically detectable nanoparticles into transparent AM media, Physical Unclonable Function (PUFs) can be embedded into AM builds and serve as an anti-counterfeiting measure. The nanoparticle selected for this work is a Quantum Dot (QD), which absorbs UV light and emits light in the visible spectrum. This unique interaction with light makes the QDs ideal for a security system since the challenge (UV light) is a different signal from the response (the visible light emitted by the QDs). PolyJet, the AM process selected for this work, utilizes inkjet to deposit a photopolymer into layers, which are then cured with a UV light. An investigation into the visibility of the QDs within the printed PolyJet media revealed that the QDs produce PUF patterns visible via fluorescent microscopy. Furthermore, rheological data shows that the ink-jetting properties of the printing media are not significantly affected by QDs in sufficient concentrations to produce PUFs. The final objective of this study is to characterize the effects of the QDs on photocuring. The mathematical model to predict the critical exposure of the QD-doped photopolymer utilizes light scattering theory, QD characterization results, and photopolymer-curing characterization results. This mathematical representation will contribute toward the body of knowledge in the area of Additive Manufacturing of nanomaterials in photopolymers. Overall, this work embodies the first investigations of the effects of QDs on rheological characteristics of ink-jetted media, the effects of QDs on curing of AM photopolymer media, visibility of nanoparticles within printed AM media, and the first attempt to incorporate security features within AM builds. Finally, the major scientific contribution of this work is the theoretical model developed to predict the effects of QDs on the curing properties of AM photopolymers. / Ph. D.

Over the last decade, there has been a tremendous growth in the number of electronic devices and applications. One of the very important aspects to deal with such proliferation of ICs is their security. Establishing the Identity (ID) of a device is the cornerstone of any secure application. Typically, the IDs of devices are stored in non-volatile memories (NVM) or through burning fuses on ICs. However, through such traditional techniques, IDs are vulnerable to attacks. Further, maintaining such secrets in NVMs is expensive. Physical Unclonable Functions (PUF) provide an alternative method for creating chip IDs. They exploit the uncontrollable variations that exist in IC manufacturing to generate identifiers. However, since PUFs exploit the small mismatch across identically designed circuits, the responses of PUFs are prone to error in the presence of unwanted variations in the operating temperature, supply voltage, and other noises. The overarching goal of this work is to develop silicon PUFs that are highly efficient and stable to such noises. In addition, to make PUFs more attractive for low cost and tiny embedded systems, our goal is to develop PUFs with minimal area and power consumption for a given ID length and security requirement. Techniques to develop such PUFs span different abstraction levels ranging from technology-independent application-level techniques to technology-dependent device-level ones. In this dissertation, we present different technology-independent and technology-dependent techniques and evaluate which techniques are good candidates for improving different qualities of PUFs. In technology-independent techniques, we propose two modifications to a conventional PUF architecture, which are detailed in this thesis. Both modifications result in a PUF that is more efficient in terms of area and power. Compared to the traditional architecture, for a given silicon real estate, the proposed architecture provides over two orders of magnitude larger $C/R$ space and it has higher resistance toward modeling attacks. Under technology-dependent methods, we investigate multiple techniques that improve stability and efficiency of PUF designs. In one approach, we propose a novel PUF design with a similar architecture to that of a traditional design, where we replace large and power hungry digital components with more efficient analog components. In another technique, we exploit the differences between pMOS and nMOS transistors in their variation of threshold voltage (Vth) and in the temperature coefficients of Vth to significantly improve the stability of bi-stable PUFs. We also use circuit-level simulations to evaluate the stability of silicon PUFs to aging degradation. We believe that our technology-independent techniques are good candidates for improving overall efficiency of PUFs in terms of both operation and implementation costs, suitable for PUFs with tight constraints on cost for design and test. However, with regards to improving the stability of PUFs, it is cost-effective to use our technology-dependent techniques as long as the extra effort for implementation and testing can be tolerated. / Ph. D.

In the context of a system design, resource-constraints refer to severe restrictions on allowable resources, while resource-efficiency is the capability to achieve a desired performance and, at the same time, to reduce wasting resources. To design for low-cost platforms, these fundamental concepts are useful under different scenarios and they call for different approaches, yet they are often mixed. Resource-constrained systems require aggressive optimizations, even at the expense of performance, to meet the stringent resource limitations. On the other hand, resource-efficient systems need a careful trade-off between resources and performance, to achieve the best possible combination. Designing systems for resource-constraints with the optimizations for resource-efficiency, or vice versa, can result in a suboptimal solution. Using modern cryptographic applications as the driving domain, I first distinguish resource-constraints from resource-efficiency. Then, I introduce the recurring strategies to handle these cases and apply them on modern cryptosystem designs. I illustrate that by clarifying the application context, and then by using appropriate strategies, it is possible to push the envelope on what is perceived as achievable, by up to two orders-of-magnitude. In the first part of this dissertation, I focus on resource-constrained modern cryptosystems. The driving application is Physical Unclonable Function (PUF) based symmetric-key authentication. I first propose the smallest block cipher in 128-bit security level. Then, I show how to systematically extend this design into the smallest application-specific instruction set processor for PUF-based authentication protocols. I conclude this part by proposing a compact method to combine multiple PUF components within a system into a single device identifier. In the second part of this dissertation, I focus on resource-efficient modern cryptosystems. The driving application is post-quantum public-key schemes. I first demonstrate energy-efficient computing techniques for post-quantum digital signatures. Then, I propose an area-efficient partitioning and a Hardware/Software codesign for its implementation. The results of these implemented modern cryptosystems validate the advantage of my approach by quantifying the drastic improvements over the previous best. / Ph. D.

The theme of the thesis is Physical Unclonable Functions (PUF). The following objectives were assigned: to provide a literature research concerning PUFs, to perform a property analysis to select appropriate type of PUF for implementation and to realize an authentication cryptosystem based on the chosen PUF. Based on the research, the cryptosystem was designed based on ring oscillator PUF. The proposed cryptosystem is tested in several scenarios with the maximal rate of successful authentication of 81%. The cryptosystem also allows to be used for device identification. Furthermore, the results were discussed and suitable improvements of design was proposed. Besides the cryptosystem itself, the thesis also introduced a unique comparison of existing types of PUFs.

Physical Unclonable Functions are a unique class of circuits that leverage the inherentvariations in manufacturing process to create unique,unclonableIDs and secret keys.The distinguishing feature of PUFs is that even an untrusted foundry cannot create a copy of the circuit as it is impossible to control the manufacturing process variations.PUFs can operate reliably in presence of voltage and temperature variations. In thisthesis, weexplorethe security offered by PUFs and tradeoffs between different metrics such as uniqueness, reliability and energy consumption.Benefits of sub-threshold PUF operation and the use of delay based Arbiter PUFs and ring oscillator PUFs in low power applications is evaluated. As we scale into lower technology nodes, there exists sufficient inter chip variation that enables each IC to be identified securely.The impact of scaling on the identification capabilities of a PUF and its reliability has been demonstrated in this work by analyzing the behavior of an Arbiter PUF in 45nm, 32nm and 22nm technology nodes. Further,the Arbiter PUF design has been implemented on a test-chip and fabricated using 45nm industry models andresults from post silicon validation are presented. Finally, we investigate a new class of PUF circuits in this work, that provide better security against machine learning based software modeling attacks. The strong identification capabilities and sufficiently high reliability offered by these PUF circuits make them promising candidates for future applications requiring securehardware cryptographic primitives.

No description available.

In recent years, there has been a drastic increase in the prevalence of counterfeiting within the electronics supply chain. At the same time, high-end commercial off-the-shelf components like FPGAs and expensive peripherals are making their way onto printed circuit boards. Manufacturers of such PCBs lose billions of dollars as well as their reputation when counterfeiting incidents are revealed within their supply chain. Moreover, there are several safety and security implications of using PCBs with counterfeit components. In this context, it is useful to enable remote integrity checking of these PCBs to identify and mitigate any safety or security concerns when they are deployed. Typical integrity checks look for the presence of an identifier embedded within a secure memory on the PCB. This approach is now being replaced by hardware intrinsic identifiers based on Physical Unclonable Functions or PUFs. Such identifiers can be used to establish trust within any component on a PCB. In this thesis, we present two PUF based protocols for remote integrity checking of PCBs by Manufacturers or end users. We propose one of the protocols for a special case of remote integrity checking - the Third Party Verification. The protocols are demonstrated using prototypes running on two different platforms - Altera DE2-115 and TI MSP430. Finally, we evaluate their performance on these prototypes and determine the feasibility of their use. / Master of Science

Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to create but impossible to duplicate. They offer solutions to many of the FPGA (Field Programmable Gate Array) issues like intellectual property, chip authentication, cryptographic key generation and trusted computing. Moreover, FPGA evolving as an important platform for flexible logic circuit, present an attractive medium for PUF implementation to ensure its security. In this thesis, we explore the behavior of RO-PUF (Ring Oscillator Physical Unclonable Functions) on FPGA when subjected to low voltages. We investigate its stability by applying environmental variations, such as temperature changes to characterize its effectiveness. It is shown with the help of experiment results that the spread of frequencies of ROs widens with lowering of voltage and stability is expected. However, due to inherent circuit challenges of FPGA at low voltage, RO-PUF fails to generate a stable response. It is observed that more number of RO frequency crossover and counter value fluctuation at low voltage, lead to instability in PUF. We also explore different architectural components of FPGA to explain the unstable nature of RO-PUF. It is reasoned out that FPGA does not sustain data at low voltage giving out unreliable data. Thus a low voltage FPGA is required to verify the stability of RO-PUF. To emphasize our case, we look into the low power applications research being done on FPGA. We conclude that FPGA, though flexible, being power inefficient, requires optimization on architectural and circuit level to generate stable responses at low voltages. / Master of Science