Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to create but impossible to duplicate. They offer solutions to many of the FPGA (Field Programmable Gate Array) issues like intellectual property, chip authentication, cryptographic key generation and trusted computing. Moreover, FPGA evolving as an important platform for flexible logic circuit, present an attractive medium for PUF implementation to ensure its security. In this thesis, we explore the behavior of RO-PUF (Ring Oscillator Physical Unclonable Functions) on FPGA when subjected to low voltages. We investigate its stability by applying environmental variations, such as temperature changes to characterize its effectiveness. It is shown with the help of experiment results that the spread of frequencies of ROs widens with lowering of voltage and stability is expected. However, due to inherent circuit challenges of FPGA at low voltage, RO-PUF fails to generate a stable response. It is observed that more number of RO frequency crossover and counter value fluctuation at low voltage, lead to instability in PUF. We also explore different architectural components of FPGA to explain the unstable nature of RO-PUF. It is reasoned out that FPGA does not sustain data at low voltage giving out unreliable data. Thus a low voltage FPGA is required to verify the stability of RO-PUF. To emphasize our case, we look into the low power applications research being done on FPGA. We conclude that FPGA, though flexible, being power inefficient, requires optimization on architectural and circuit level to generate stable responses at low voltages. / Master of Science

With the importance of data security at its peak today, many reconfigurable systems are used to provide security. This protection is often provided by FPGA-based encrypt/decrypt cores secured with secret keys. Physical unclonable functions (PUFs) use random manufacturing variations to generate outputs that can be used in keys. These outputs are specific to a chip and can be used to create device-tied secret keys. Due to reliability issues with PUFs, key generation with PUFs typically requires error correction techniques. This can result in substantial hardware costs. Thus, the total cost of a $n$-bit key far exceeds just the cost of producing $n$ bits of PUF output. To tackle this problem, we propose the use of variation aware intra-FPGA PUF placement to reduce the area cost of PUF-based keys on FPGAs. We show that placing PUF instances according to the random variations of each chip instance reduces the bit error rate of the PUFs and the overall resources required to generate the key. Our approach has been demonstrated on a Xilinx Zynq-7000 programmable SoC using FPGA specific PUFs with code-offset error correction based on BCH codes. The approach is applicable to any PUF-based system implemented in reconfigurable logic. To evaluate our approach, we first analyze the key metrics of a PUF - reliability and uniqueness. Reliability is related to bit error rate, an important parameter with respect to error correction. In order to generate reliable results from the PUFs, a total of four ZedBoards containing FPGAs are used in our approach. We quantify the effectiveness of our approach by implementing the same key generation scheme using variation-aware and default placement, and show the resources saved by our approach.

No description available.

The introduction of Physical Unclonable Functions (PUFs) and lightweight consensus algorithms to aid in the bolstering of security and privacy in both IoT and IoE does show a great deal of promise not only in these areas, but in resource cost over traditional methods of blockchain.  However, several previous studies make claims regarding performance of novel solutions without providing detailed information as to the physical components of their experiments.  This comparative study shows that Proof of Authentication (PoAh) performs the best out of three selected consensus algorithms and that the claims made regarding the performance of PUFChain and Proof of PUF-enabled Authentication (PoP) could not be replicated in this instance.

The dissertation thesis deals with cryptographic protocols for secure authentication of communicating parties, which are intended primarily for low-cost devices used in Internet of Things. Low-cost devices represent computationally, memory and power constrained devices. The thesis focuses mainly on the possibilities of using mathematically undemanding cryptographic resorces for ensuring integrity of transmitted dat, authenticity of and secured transmission of data on low-cost devices. The main goals of the thesis focus on the design of new advanced cryptographic protocols for ensuring integrity of transmitted data, authenticity, confidentiality of transmitted data between low-cost devices and authenticity with non-repudiation of done events. The thesis describes proposal of three authentication protocols, one unilateral authentication protocol and two mutual authentication protocols. The thesis also describes proposals of two protocols for secured transmission of data between two devices, one protocol without a proof of receipt data and one protocol with proof of receipt data. In this thesis is also performed a security analysis and a discussion to proposed protocols.

No description available.

Modern cities are undergoing rapid expansion. The number of connected devices in the networks in and around these cities is increasing every day and will exponentially increase in the next few years. At home, the number of connected devices is also increasing with the introduction of home automation appliances and applications. Many of these appliances are becoming smart devices which can track our daily routines. It is imperative that all these devices should be secure. When cryptographic keys used for encryption and decryption are stored on memory present on these devices, they can be retrieved by attackers or adversaries to gain control of the system. For this purpose, Physical Unclonable Functions (PUFs) were proposed to generate the keys required for encryption and decryption of the data or the communication channel, as required by the application. PUF modules take advantage of the manufacturing variations that are introduced in the Integrated Circuits (ICs) during the fabrication process. These are used to generate the cryptographic keys which reduces the use of a separate memory module to store the encryption and decryption keys. A PUF module can also be recon gurable such that the number of input output pairs or Challenge Response Pairs (CRPs) generated can be increased exponentially. This dissertation proposes three designs of PUFs, two of which are recon gurable to increase the robustness of the system.

No description available.

Le vol et la contrefaçon touchent toutes les sphères industrielles de nos sociétés. En particulier, les produits électroniques représentent la deuxième catégorie de produits la plus concernée par ces problèmes. Parmi les produits électroniques les plus touchés, on retrouve les téléphones mobiles, les tablettes, les ordinateurs mais aussi des éléments bien plus basiques comme des circuits analogiques ou numériques et les circuits intégrés. Ces derniers sont au coeur de la plupart des produits électroniques et un téléphone mobile peut être considéré comme contrefait s’il possède ne serait-ce qu’un seul circuit intégré contrefait. Le marché de la contrefaçon de circuits intégrés représente entre 7 et 10% du marché total des semi-conducteurs, ce qui implique une perte d’au moins 24 milliards d’euros en 2015 pour les entreprises concevant des circuits intégrés. Ces pertes pourraient s’élever jusqu’à 36 milliards d’euros en 2016. Il est donc indispensable de trouver des solutions pratiques et efficaces pour lutter contre la contrefaçon et le vol de circuits intégrés. Le projet SALWARE, financé par l’Agence Nationale de la Recherche et par la Fondation de Recherche pour l’Aéronautique et l’Espace, a pour but de lutter contre le problème de la contrefaçon et du vol de circuits intégrés et propose l’étude et la conception de matériels salutaires (ou salwares). En particulier, l’un des objectifs de ce projet est de combiner astucieusement plusieurs mécanismes de protection participant à la lutte contre la contrefaçon et le vol de circuits intégrés, pour construire un système d’activation complet. L’activation des circuits intégrés après leur fabrication permet de redonner leur contrôle au véritable propriétaire de la propriété intellectuelle. Dans ce manuscrit de thèse, nous proposons l’étude de trois mécanismes de protection participant à la lutte contre la contrefaçon et le vol de circuits intégrés. Dans un premier temps, nous étudierons l’insertion et la détection de watermarks dans les machines à états finies des systèmes numériques synchrones. Ce mécanisme de protection permet de détecter un vol ou une contrefaçon. Ensuite, une fonction physique non-clonable basée sur des oscillateurs en anneaux dont les oscillations sont temporaires est implantée et caractérisée sur FPGA. Ce mécanisme de protection permet d’identifier un circuit grâce à un identifiant unique créé grâce aux variations du processus de fabrication des circuits intégrés. Enfin, nous aborderons l’implantation matérielle d’algorithmes légers de chiffrement par bloc, qui permettent d’établir une communication sécurisée au moment de l’activation d’un circuit intégré / Counterfeiting and theft affects all industrial activities in our society. Electronic products are the second category of products most concerned by these issues. Among the most affected electronic products, we find mobile phones, tablets, computers as well as more basic elements such as analog and digital circuits or integrated circuits. These are the heart of almost all electronic products and we can say that a mobile phone is counterfeited if it has at least one counterfeit integrated circuit inside. The market of counterfeit integrated circuit is estimated between 7 and 10% of the global semi-conductors market, which represents a loss of at least 24 billion euros for the lawful industry in 2015. These losses could reach 36 billion euros in 2016. Therefore, there is an absolute necessity to find practical and efficient methods to fight against counterfeiting and theft of integrated circuits. The SALWARE project, granted by the French "Agence Nationale de la Recherche" and by the "Fondation de Recherche pour l’Aéronautique et l’Espace", aims to fight against the problem of counterfeiting and theft of integrated circuitsFor that, we propose to design salutary hardwares (salwares). More specifically,we propose to cleverly combine different protection mechanisms to build a completeactivation system. Activate an integrated circuit after its manufacturing helpsto restore the control of integrated circuits to the true owner of the intellectualproperty.In this thesis, we propose the study of three different protection mechanismsfighting against counterfeiting and theft of integrated circuits. First, the insertionand the detection of watermark in the finite state machine of digital and synchronoussystems will be studied. This mechanism helps to detect counterfeit or theftparts. Then, a physical unclonable function based on transcient effect ring oscillatoris implemented and characterized on FPGA. This protection mechanism is used toidentify integrated circuit with a unique identifier created thanks to the extractionof entropy from manufacturing process variations. Finally, we discuss the hardwareimplementations of lightweight block ciphers, which establish a secure communicationduring the activation of an integrated circuit

La conception de circuits intégrés est aujourd'hui une tâche extrêmement complexe. Cela pousse les concepteurs à adopter une approche modulaire, où chaque bloc fonctionnel est décrit de manière indépendante. Ces blocs fonctionnels, appelés composants virtuels, sont vendus par leurs concepteurs à des intégrateurs système qui les utilisent dans des projets complexes. Cette division a pour conséquence une hausse inquiétante des cas de copie illégale des composants virtuels. Afin de lutter contre cette menace sur la propriété intellectuelle des concepteurs, l'objectif de cette thèse était de mettre au point un système complet d'activation à distance de composants virtuels, permettant au concepteur de savoir exactement combien de composants virtuels sont effectivement utilisés. Pour cela, les deux premières contributions de cette thèse portent sur la modification de la logique combinatoire d'un composant virtuel afin de le rendre activable. La première méthode permet de forcer les sorties à une valeur fixe de manière contrôlée. La seconde est une technique efficace de sélection de nœuds à altérer, encore une fois de manière contrôlée, afin de rendre le composant virtuel temporairement inutilisable. La troisième contribution de cette thèse est une méthode légère de correction d'erreurs à appliquer aux réponses issues des fonctions physiques non-clonables, qui constituent un identifiant intrinsèque des instances du composant virtuel. Réutilisant un protocole de correction d'erreurs issu de l'échange quantique de dés, cette méthode est beaucoup plus légère que les codes correcteurs d'erreurs classiquement utilisés pour cette application / Designing integrated circuits is now an extremely complex task. This is why designers adopt a modular approach, where each functional block is described independently. These functional blocks, called intellectual property (IP) cores, are sold by their designers to system integrators who use them in complex projects. This division led to the rise of cases of illegal copying of IP cores. In order to fight this threat against intellectual property of lP core designers, the objective of this PhD thesis was to develop a secure remote activation scheme for IP cores, allowing the designer to know exactly how many IP cores are currently used. To achieve this, the first two contributions of thesis thesis deal with the modification of combinational logic of an IP core to make it activable. The first method allows to controllably force the outputs to a fixed logic value. The second is an efficient technique to select the nodes to controllably alter, so that the IP core is temporarily unusable. The third contribution of this thesis is a lightweight method of error correction to use with PUF (Physical Undonable Functions) responses, which are an intrinsic identifier of instances of the lP core. Reusing an error-correction protocol used in quantum key ex.change, this method is much more lightweight than error-correcting