Power line communications (PLC) as applied to electrical power grid is known since long; however, PLC in microprocessors was recently introduced by VTVT Lab. Since power distribution network (PDN) inside a microprocessor is ubiquitous, therefore, any node inside a microprocessor can be accessed by attaching a simple communication circuit to it. The scheme is extremely attractive as it avoids the routing overhead of the data-path between an internal node and an I/O pin. A number of applications are possible for PLC in microprocessors such as on-line testing, monitoring/control of internal nodes, fault diagnosis etc.
Feasibility of the PLC approach has been extensively studied by earlier researchers at VTVT. The feasibility studies investigated the frequency response of a microprocessor's PDN and looked for existence of passbands — frequency bands where signal attenuation through the PDN is small. Two different approaches were followed—the first approach employed analytical modeling of the high frequency characteristics of the PDN, while the second approach conducted measurements on Intel® microprocessors' PDN. Although, differences were observed in the results of the two approaches; both the approaches demonstrated existence of passbands, thus affirming the feasibility of the PLC scheme.
This thesis presents a system level study conducted to estimate performance of the PLC scheme. Measurement results were used to model the PDN channel. The study provides useful insights for the design of microprocessor level PLC system. Specifically, the study estimates optimal pulse width required to maximize the system performance and the range of achievable data-rates. The study demonstrates that it is feasible to communicate data through a microprocessor's PDN without inducing large disturbances on the power line.
The other work presented in this thesis is the design of low power receiver for microprocessor level PLC, also called data recovery block. The proposed design of data recovery block employs Correlation Detection (CD) receiver architecture. The design has been implemented in IBM 0.13 µm CMOS process and has been verified to operate reliably across Process, Voltage and Temperature variations. The design has a small foot-print of 300 µm x 160 µm and consumes 3.58 mW while operating from 1.2 V power supply. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/35325 |
| Date | 14 October 2009 |
| Creators | Chawla, Vipul |
| Contributors | Electrical and Computer Engineering, Ha, Dong Sam, Tront, Joseph G., Schaumont, Patrick R. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | Chawla_V_T_2009.pdf |
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