This thesis presents the design, implementation and fabrication for a 0.13μm interface to a capacitive MEMS accelerometer.
By varying the number of amplifier slices used in concurrence based on different full scale input ranges, the analog circuitry power scales as the input range scales. Due to the oversampling nature of typical accelerometer front ends, for a full-scale input increase of N times, the analog circuitry power reduces by N2 times. The front end has two signal amplification stages, with the first stage power scaled. The chip is 1.15mmx1.15mm and implemented in a 0.13μm CMOS process. The design was packaged with the MEMS accelerometer chip inside a 44 pin CQFP. Measured results show an output rms noise of 63μVrms in a 100Hz bandwidth. The total analog circuitry power scales very linearly with different full scale ranges.
A novel simple offset removal network is also shown and confirmed via measurement results.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/35144 |
| Date | 19 March 2013 |
| Creators | Tse, Colin |
| Contributors | Johns, David A. |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
Page generated in 0.0018 seconds