This thesis presents the design, implementation and fabrication for a 0.13μm interface to a capacitive MEMS accelerometer. By varying the number of amplifier slices used in concurrence based on different full scale input ranges, the analog circuitry power scales as the input range scales. Due to the oversampling nature of typical accelerometer front ends, for a full-scale input increase of N times, the analog circuitry power reduces by N2 times. The front end has two signal amplification stages, with the first stage power scaled. The chip is 1.15mmx1.15mm and implemented in a 0.13μm CMOS process. The design was packaged with the MEMS accelerometer chip inside a 44 pin CQFP. Measured results show an output rms noise of 63μVrms in a 100Hz bandwidth. The total analog circuitry power scales very linearly with different full scale ranges. A novel simple offset removal network is also shown and confirmed via measurement results.

This thesis presents the design, implementation and fabrication for a 0.13μm interface to a capacitive MEMS accelerometer. By varying the number of amplifier slices used in concurrence based on different full scale input ranges, the analog circuitry power scales as the input range scales. Due to the oversampling nature of typical accelerometer front ends, for a full-scale input increase of N times, the analog circuitry power reduces by N2 times. The front end has two signal amplification stages, with the first stage power scaled. The chip is 1.15mmx1.15mm and implemented in a 0.13μm CMOS process. The design was packaged with the MEMS accelerometer chip inside a 44 pin CQFP. Measured results show an output rms noise of 63μVrms in a 100Hz bandwidth. The total analog circuitry power scales very linearly with different full scale ranges. A novel simple offset removal network is also shown and confirmed via measurement results.

LOW power operation for wireless radio receivers has been gaining importance lately on account of the recent spurt of growth in the usage of ubiquitous embedded mobile devices. These devices are becoming relevant in all domains of human influence. In most cases battery life for these devices continue to be an us-age bottleneck as energy storage techniques have not kept pace with the growing demand of such mobile computing devices. Many applications of these radios have limitations on recharge cycle, i.e. the radio needs to last out of a battery for long duration. This will specially be true for sensor network applications and for im-plantable medical devices. The search for low power wireless receivers has become quite advanced with a plethora of techniques, ranging from circuit to architecture to system level approaches being formulated as part of standard design procedures. However the next level of optimization towards “Smart” receiver systems has been gaining credence and may prove to be the next challenge in receiver design and de-velopment. We aim to proceed further on this journey by proposing Power Scalable Wireless Receivers (PSRX) which have the capability to respond to instantaneous performance requirements to lower power even further. Traditionally low power receivers were designed for worst-case input conditions, namely low signal and high interference, leading to large dynamic range of operation which directly im-pacts the power consumption. We propose to take into account the variation in performance required out of the receiver, under varying Signal and Interference conditions, to trade-off power. We have analyzed, designed and implemented a Power Scalable Receiver tar-geted towards low data-rate receivers which can work for Zigbee or Bluetooth Low Energy (BLE) type standards. Each block of such a receiver system was evaluated for performance-power trade-offs leading to identification of tuning/control knobs at the circuit architecture level of the receiver blocks. Then we developed an usage algorithm for finding power optimal operational settings for the tuning knobs, while guaranteeing receiver reception performance in terms of Bit-Error-Rate (BER). We have proposed and demonstrated a novel signal measurement system to gen-erate digitized estimates of signal and interference strength in the received signal, called Received Signal Quality Indicator (RSQI). We achieve a RSQI average energy consumption of 8.1nJ with a peak energy consumption of 9.4nJ which is quite low compared to the packet reception energy consumption for low power receivers, and will be substantially lower than the energy savings which will be achieved from a power scalable receiver employing a RSQI. The full PSRX system was fabricated in UMC 130nm RF-CMOS process to test out our concepts and to formally quantify the power savings achieved by following the design methodology. The test chip occupied an area of 2.7mm2 with a peak power consumption of 5.5mW for the receiver chain and 18mW for the complete PSRX. We were able to meet the receiver performance requirements for Zigbee standard and achieved about 5X power savings for the range of input condition variations.

Sensor nodes in a sensor network is power constrained. Transceiver electronics of a node in sensor network consume a good share of total power consumed in the node. The thesis proposes receiver architecture and algorithms which reduces power consumption of the receiver. The work in the thesis ranges from designing low power architecture of the receiver to experimentally verifying the functioning of the receiver. Concepts proposed in the thesis are: Low power adaptive architecture :-A baseband digital receiver design is proposed which changes its sampling frequency and bit-width based on interference detection and SNR estimation. The approach is based on Look-up-table (LUT) in the digital section of the receiver. Interference detector and SNR estimator has been proposed which suits this approach. Settings of different sections of digital receiver changes as sampling frequency and bit-width varies. But, this change in settings ensures that the desired BER is achieved. Overall, the receiver reduces amount of processing when conditions are benign and does more processing when conditions are not favorable. It is shown that the power consumption by the digital baseband can be reduced by 85% (7 times) when there is no interference and SNR is high. Thus the proposed design meets our requirement of low power hardware. The design is coded in Verilog HDL and power and area estimation is done using Synopsys tools. Faster Simulation Methodologies :-Usually physical layer simulations are done on baseband equivalent model of the signal in the receiver chain. Simulating Physical layer algorithms on bandpass signals for BER evaluation is very time consuming. We need to do the bandpass simulations to capture the effect of quantization on bandpass signal in the receiver. We have developed a variance measuring simulation methodology for faster simulation which reduces simulation time by a factor of 10. Low power, Low area, Non-coherent, Non-data-aided joint tracking and acquisition algorithm :-Correlation is a very popular function used particularly in synchronization algorithms in the receivers. But correlation requires usage of multipliers. Multipliers are area and power consuming blocks. A very low power and low area joint tracking and acquisition algorithm is developed. The algorithm does not use any multiplier to synchronize. Even it avoids squaring and adding the signals to achieve non-coherency. Beside the algorithm is non-data-aided as well and does not require ROM to store the sequence. The Algorithm saves area/power of existing similar algorithms by 90%. Experimental setup for performance evaluation of the receiver :-The developed baseband architecture and algorithms are experimentally verified on a wireless test setup. Wireless test setup consists of FPGA board, VSGs, Oscilloscopes, Spectrum analyzer and a discrete component RF board. Packet error and packet loss measurement is done by varying channel conditions. Many practical and interesting issues dealing with wireless test setup infrastructure were encountered and resolved.