Over the last few decades, the susceptibility of integrated circuits to electrostatic discharge (ESD) induced damages has justified the use of dedicated on-chip protection circuits. Design of robust protection circuits remains a challenging task because ESD failure mechanisms have become more acute as device dimensions continue to shrink. A lack of understanding of the ESD phenomena coupled with the increased sensitivity of smaller devices and time-to-market demands has led to a trial-and-error approach to ESD-protected circuit design. Improved analysis capabilities and a systematic design approach are essential to accomplish the challenging task of providing adequate protection to core circuit(s).
The design of ESD protection circuitry for RFIC's has been relatively slow to evolve, compared to their digital counterparts, and is now emerging as a new design challenge in RF and high-speed mixed-signal IC development. Sub-circuits which are not embedded in a single System-on-Chip (SOC), such as RF Power amplifiers (PAs), are of particular concern as they are more susceptible to the various ESD events.
This thesis presents the development of integrated ESD protection circuitry for two RFIC Power Amplifier designs. A prototype PA for 2.4 GHz Wireless Local Area Network (WLAN) applications was redesigned to provide protection to the RF input and the PA Control pins. A relatively new technique known as the L-C tank approach was used to protect the RFinput while a standard diode ring approach was used to protect the control line. The protection techniques studied were subsequently extended to a completely protected three-stage PA targeting 1.9 GHz Digitally Enhanced Cordless Telephone (DECT) applications. An on-chip shunt-L-series-C input matching network was used to provide ESD protection to the input pin of the DECT PA. A much more area efficient (as compared to the diode ring technique) Zener diode approach was used to protect the control and signal lines. The PA's RF performance was virtually unaffected by the addition of the protection circuits.
Both PAs were designed in a commercially available 0.5 ìm SiGe-HBT process. The partially protected WLAN PA was fabricated and packaged in a 3mm x 3mm Fine Pitch Quad Flat Package FQFP-N 12 Lead package and had a measured ESD protection rating of ± 1kV standard Human Body Model (HBM) ESD test. The simulated DECT PA demonstrated +1.5kV/-4kV HBM performance. / Master of Science
| Identifer | oai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/31705 |
| Date | 27 April 2005 |
| Creators | Muthukrishnan, Swaminathan |
| Contributors | Electrical and Computer Engineering, Raman, Sanjay, Bostian, Charles W., Tront, Joseph G. |
| Publisher | Virginia Tech |
| Source Sets | Virginia Tech Theses and Dissertation |
| Detected Language | English |
| Type | Thesis |
| Format | application/pdf |
| Rights | In Copyright, http://rightsstatements.org/vocab/InC/1.0/ |
| Relation | swami_thesis_final.pdf |
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