This thesis presents the CMOS integer-N frequency synthesizer for 2 GHz 802.11 WLAN applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a loop filter, and a pulse-swallow counter. In pulse-swallow counter, we use less numbers of transistors divide-by-2/3 prescaler to work in high frequency in order to reduce power consumption. We complete the design of pulse-swallow counter for 2-GHz (seven channels) and the 5-GHz (four channels) application. The average power consumption of pulse-swallow counter is 2.49 mW and 2.98 mW for 2-GHz and 5-GHz application respectively. We use Verilog-A language to complete VCO behavior model for frequency synthesizer and utilize the Spectre simulation results justify the feasibility of our proposed frequency synthesizer. The total power consumption of frequency synthesizer is 3.432mW and 4.673mW for 2-GHz and 5-GHz frequency synthesizer, respectively.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0721106-144223 |
| Date | 21 July 2006 |
| Creators | Wu, Feng-Ji |
| Contributors | Shen-Fu Hsiao, Shiann-Rong Kuang, Huei-Yung Lin, Ko-Chi Kuo |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0721106-144223 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0021 seconds