In this thesis, we propose a three-dimensional (3D) fold-up non-classical unipolar complementary metal-oxide semiconductor field-effect transistor (CMOS-FET) structure and its operation mechanism. We utilize a NMOS transistor having punch-through effect and a classical NMOS to realize our proposed CMOS circuit. In our proposed CMOS circuit, both driver and load transistors are based on the n-channel MOS (NMOS) structures, so, in this unipolar CMOS, the carrier used is the electron only. Hence, the delay time can be improved by 14% when compared with the conventional CMOS. Moreover, the p-channel MOS (PMOS) transistor can be eliminated in our proposed CMOS circuit. Thus, we do not need the traditional N-well technique and we also use the 3D device architecture to drastically reduce the total device area more than 69%, in comparison to a conventional CMOS. If our proposed CMOS architecture is implemented in the VLSI circuits, the packing density can be increased and the device fabrication cost can also be reduced significantly. Therefore, our proposed 3D fold-up non-classical single-carrier CMOS-FET can achieve three important requirements as follows: 1) area reduction, 2) enhanced speed, and 3) decrease cost in the system fabrication.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0730110-144809 |
| Date | 30 July 2010 |
| Creators | Kuo, Chih-hao |
| Contributors | Albert Chin, Jyi-Tsong Lin, Yao-Tsung Tsai, Meng-Hsueh Chiang, Wen-Kuan Yeh |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0730110-144809 |
| Rights | not_available, Copyright information available at source archive |
Page generated in 0.0016 seconds