In this thesis, we propose a three-dimensional (3D) fold-up non-classical unipolar complementary metal-oxide semiconductor field-effect transistor (CMOS-FET) structure and its operation mechanism. We utilize a NMOS transistor having punch-through effect and a classical NMOS to realize our proposed CMOS circuit. In our proposed CMOS circuit, both driver and load transistors are based on the n-channel MOS (NMOS) structures, so, in this unipolar CMOS, the carrier used is the electron only. Hence, the delay time can be improved by 14% when compared with the conventional CMOS. Moreover, the p-channel MOS (PMOS) transistor can be eliminated in our proposed CMOS circuit. Thus, we do not need the traditional N-well technique and we also use the 3D device architecture to drastically reduce the total device area more than 69%, in comparison to a conventional CMOS. If our proposed CMOS architecture is implemented in the VLSI circuits, the packing density can be increased and the device fabrication cost can also be reduced significantly. Therefore, our proposed 3D fold-up non-classical single-carrier CMOS-FET can achieve three important requirements as follows: 1) area reduction, 2) enhanced speed, and 3) decrease cost in the system fabrication.

In this paper, we propose a novel Unipolar CMOS device in which the transport carriers are electron only. And we achieve good inverter output waveform and logic circuit applications by simulation. Duo to all n-channel (NMOS) structures are used, we call this proposed CMOS as a Unipolar CMOS. A new basic theory of utilizing the punch through effect is demonstrated to enhance the tPLH in our proposed Unipolar CMOS. The average delay time compared with the classical CMOS circuit can be improved 23% for high-performance applications. For our proposed Unipolar CMOS, all n-channel MOS are used to eliminate the N- and P-well processes and ignore the difference between the carrier mobility. In addition, the common electrodes are also exploited, hence, the layout area can be reduced to about 75%, which leads to significantly increase the packing density of CMOS circuits in the same chip.

In this thesis, we propose a high density non-classical unipolar CMOS width two embedded oxide (2EO) NMOS load. The words ¡§unipolar CMOS¡¨ refer to the fact that the conventional NMOS driver and the proposed 2EO NMOS load are presented in which the electron is the only carrier used. Among them, the 2EO scheme is used to isolate the inversion current. And the dominant current in the 2EO NMOS load is the punch through current which is not a destructive current mechanism. Our proposed CMOS, due to the same carrier used, does not have to compensate the layout width in load design. In addition, the shared terminal of output contacts and the elimination of N-well technique are also presented in our proposed CMOS. Therefore, the layout area can be reduced 72%, in comparison with conventional CMOS. Furthermore, the packing density can be increased and the fabrication cost can be reduced, respectively. We also find out that the delay time can be improved 39% to increase the operating frequency, as compared with the convention CMOS.

In this thesis, we present a high-speed non-classical unipolar CMOS with a thick sidewall-spacer gate-oxide NMOS load. This unipolar CMOS is composed of a NMOS driver and a thick sidewall-spacer gate-oxide NMOS which replaces a PMOS as load. We focus on the investigation of punch-through current in unipolar CMOS trends. In addition, we also design a conventional CMOS for comparison. According to the simulations, the logical characteristics of our proposed CMOS are valid, in which the average propagation delay time is improved 20 % compared with the conventional CMOS. This is due to the presence of a thick sidewall-spacer gate-oxide NMOS load. For the viewpoint of device fabrication, the N well process can also be eliminated. This means that the proposed NMOS load not only improves the CMOS speed, but also reduces the fabrication cost. Thus, because of the shared-terminal output, the layout area can be significantly decreased 41 %, in comparison with the conventional CMOS.