Continued scaling of CMOS devices with Si and SixGe1-x down to 22 nm design node or beyond will require the formation of ever shallower and more abrupt junctions with higher doping levels in order to manage the short channel effects. With the increasing importance of surface proximity and stress effects, the lateral diffusion in gate-extension overlap region strongly influences both threshold voltage roll-off degradation and DIBL increase by requiring an optimized abruptness and diffusion for better device performance. Therefore, the detailed understanding of defect-dopant interactions in the disordered and/or strained systems is essential to develop a predictive kinetic model for the evolution of dopant concentration and electrical activation profiles. Our density functional theory calculations provide the guidance for experimental designs to realize ultra-shallow junction formation required for future generations of nano-scale CMOS devices.
Few systematic studies in epitaxially-grown SixGe1-x channel CMOS have been reported. The physical mechanisms of boron diffusion in strained SixGe1-x/Si heterojunction layers with different SixGe1-x layer thicknesses and Ge content (>50%) are addressed, especially with high temperature annealing. In addition, the effects of the fluorine incorporated during BF2 implant on boron diffusion are investigated to provide more insight into short channel device design. In this study, we investigate how short channel margins are affected by Ge mole fraction and SixGe1-x layer thickness in a compressively strained SixGe1-x/Si heterojunction PMOS with high temperature annealing.
Series resistance characterization in S/D extension region and gate oxide interface trap characterization for Si, SixGe1-x, and Ge nMOSFETs are done. TCAD device simulation is also performed to evaluate which distributions of interface traps will significantly affect the electrical characteristics such as flatband voltage (VFB) shift and threshold voltage (Vth) shift based on capacitance-voltage (CV) and current-voltage (IV) curves. n+/p and p+/n diode structures are studied in order to decouple the electrical characteristics from the gated-diode (GD) MOSFETs. With the extraction of S/D series resistance from various channel lengths, possible reasons for performance degradation in SixGe1-x and Ge nMOSFETs, based on simulations, are proposed. / text
| Identifer | oai:union.ndltd.org:UTEXAS/oai:repositories.lib.utexas.edu:2152/ETD-UT-2010-05-739 |
| Date | 03 September 2010 |
| Creators | Kim, Yonghyun |
| Source Sets | University of Texas |
| Language | English |
| Detected Language | English |
| Type | thesis |
| Format | application/pdf |
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