Two novel clock feedthrough compensation circuits for switched - current (SI) memory cells
are proposed to reduce the clock feedthrough error. One is a current compensation first generation
SI memory cell and another is an error voltage reduction second generation SI memory cell.
Both circuits are designed using a 0.5£gm UMC CMOS process. In this study, the first circuit
has obtained an accuracy about 0.1% error with a frequency of 5MHz, and the second circuit has
achieved 0.12% error in accuracy with 10.5MHz in frequency. The results are obtained by SPICE
simulates.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0726100-200736 |
| Date | 26 July 2000 |
| Creators | Chang-Chan, Sun-Yu |
| Contributors | Chia-Hsiung Kao, Jinn-Shyan Wang, Shyh-Jye Jou, Jyi-Tsong Lin, Yao-Tsung Tsai |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | English |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726100-200736 |
| Rights | unrestricted, Copyright information available at source archive |
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