The aim of this master’s thesis is to implement an ADC (Analog-to-Digital Converter) foraudio applications using external components together with an FPGA (Field-ProgrammableGate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bitresolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually someunused pins and logic available in the FPGA that can be used for other purposes. This istaken advantage of, to make the ADC as low-cost as possible.This thesis presents two solutions: (1) a - (Sigma-Delta) converter with a first order passive loop-filter and (2) a - converter with a second order active loop-filter. The solutionshave been designed on a PCB (Printed Curcuit Board) with a Xilinx Spartan-6 FPGA. Bothsolutions take advantage of the LVDS (Low-Voltage-Differential-Signaling) input buffers inthe FPGA.(1) achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Effectivenumber of bits) 10.06 bits) and (2) achieves a peak SNDR of 80.3 dB (ENOB 13.04). (1) isvery low-cost ($0.06) but is not suitable for high-precision audio applications. (2) costs $0.53for mono audio and $0.71 for stereo audio and is comparable with the solution used today:an external ADC (PCM1807).
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-96009 |
| Date | January 2013 |
| Creators | Hellman, Johan |
| Publisher | Linköpings universitet, Elektroniksystem, Linköpings universitet, Tekniska högskolan |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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