With a reference specification model in terms of 8 GS/s Sigma Delta Modulator in a 28 nm CMOS process consuming 890 mW, the purpose with this thesis is to construct a similar and simpler model but with higher specification demands. In a 22 nm SOI process with an input signal bandwidth of 500 MHz sampled at 16 GS/s with a power consumption below 2 W, the objective is to design a Continuous-Time Sigma Delta Modulator with verified simulated functionality on a transistor level basis. This specification is accomplished - with a power consumption in total of 75 mW. The design methodology is divided into an integrator part along with a quantizer and feedback DAC part. A top-down strategy is carried out starting with an ideal high level Verilog-A model for the complete system, followed by a hardware implementation on transistor level.
| Identifer | oai:union.ndltd.org:UPSALLA1/oai:DiVA.org:liu-155781 |
| Date | January 2018 |
| Creators | Öberg, Eric, Kindeskog, Gustav |
| Publisher | Linköpings universitet, Tekniska fakulteten, Linköpings universitet, Elektroniska Kretsar och System, Linköpings universitet, Tekniska fakulteten, Linköpings universitet, Elektroniska Kretsar och System |
| Source Sets | DiVA Archive at Upsalla University |
| Language | English |
| Detected Language | English |
| Type | Student thesis, info:eu-repo/semantics/bachelorThesis, text |
| Format | application/pdf |
| Rights | info:eu-repo/semantics/openAccess |
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