The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the system integration level is low. Moderntransceivers shift many of these tasks to digital domain, wherethe filtering and channel selection can be realized moreaccurately and more compactly. However the price for the highintegration level is the critical requirement on the ADC,because the simplified analog part sends not only the weaksignal but also the unwanted strong neighboring channel to theADC. In order to digitize the needed signal in the presence ofstrong disturbances, a high dynamic-range and high-speed ADC isneeded. Sigma Delta ADCs are promising candidates for A/D conversionin modern wireless transceivers. They are naturally suitablefor high-resolution narrow-band A/D conversions. With thedevelopment of processing and design techniques, sigma deltaADCs are expanding their applications to moderate-band area,such as wireless communication baseband processing. Currentlymobile communication systems are migrating from 2G to 3G. In 2Gsystems the baseband width is in the order of hundred kHz,while in 3G systems the baseband width is in the order of MHz.To face the challenge of designing a high resolution sigmadelta ADC with large bandwidth, a multi-bit internal quantizeris often used. In this thesis special design considerations onmulti-bit sigma delta modulators are discussed. The biggestdrawback of multi-bit sigma delta modulators isthe need of anextra circuit to attenuate or compensate the internal multi-bitDAC non-linearity. This thesis provides a comprehensiveanalysis of the solution which combines a multi-bit quantizerwith a 1-bit DAC in a sigma delta modulator. The theoreticalanalysis result is verified by measurement results. Anothertopic addressed in the thesis is how to reduce the multi-bitquantizer complexity. It is shown that by using a semiuniformquantizer, the quantizer can reduce its complexity by one-bityet still maintain the same modulator dynamic range. Theperformance of the semi-uniform quantizer is also verified bymeasurement results.

<p>The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the system integration level is low. Moderntransceivers shift many of these tasks to digital domain, wherethe filtering and channel selection can be realized moreaccurately and more compactly. However the price for the highintegration level is the critical requirement on the ADC,because the simplified analog part sends not only the weaksignal but also the unwanted strong neighboring channel to theADC. In order to digitize the needed signal in the presence ofstrong disturbances, a high dynamic-range and high-speed ADC isneeded.</p><p>Sigma Delta ADCs are promising candidates for A/D conversionin modern wireless transceivers. They are naturally suitablefor high-resolution narrow-band A/D conversions. With thedevelopment of processing and design techniques, sigma deltaADCs are expanding their applications to moderate-band area,such as wireless communication baseband processing. Currentlymobile communication systems are migrating from 2G to 3G. In 2Gsystems the baseband width is in the order of hundred kHz,while in 3G systems the baseband width is in the order of MHz.To face the challenge of designing a high resolution sigmadelta ADC with large bandwidth, a multi-bit internal quantizeris often used. In this thesis special design considerations onmulti-bit sigma delta modulators are discussed. The biggestdrawback of multi-bit sigma delta modulators isthe need of anextra circuit to attenuate or compensate the internal multi-bitDAC non-linearity. This thesis provides a comprehensiveanalysis of the solution which combines a multi-bit quantizerwith a 1-bit DAC in a sigma delta modulator. The theoreticalanalysis result is verified by measurement results. Anothertopic addressed in the thesis is how to reduce the multi-bitquantizer complexity. It is shown that by using a semiuniformquantizer, the quantizer can reduce its complexity by one-bityet still maintain the same modulator dynamic range. Theperformance of the semi-uniform quantizer is also verified bymeasurement results.</p>

The sigma-delta modulator is a popular signal amplitude quantization error (or noise) shaper used in oversampling analogue-to-digital and digital-to-analogue converter systems. The shaping of the noise frequency spectrum is performed by feeding back the quantization errors through a time delay element filter and feedback loop in the circuit, and by the addition of a possible stochastic dither signal at the quantizer. The aim in audio systems is to limit audible noise and distortions in the reconverted analogue signal. The formulation of the sigma-delta modulator as a discrete dynamical system provides a useful framework for the mathematical analysis of such a complex nonlinear system, as well as a unifying basis from which to consider other systems, from pseudorandom number generators to stochastic resonance processes, that yield equivalent formulations. The study of chaos and other complementary aspects of internal dynamical behaviour in previous research has left important issues unresolved. Advancement of this study is naturally facilitated by the dynamical systems approach. In this thesis, the general order feedback/feedforward sigma-delta modulator with multi-bit quantizer (no overload) and general input, is modelled and studied mathematically as a dynamical system. This study employs pertinent topological methods and relationships, which follow centrally from the symmetry of the circle map interpretation of the error state space dynamcis. The main approach taken is to reduce the nonlinear system into local or special case linear systems. Systems of sufficient structure are shown to often possess structured random, or random-like behaviour. An adaptation of Devaney's definition of chaos is applied to the model, and an extensive investigation of the conditions under which the associated chaos conditions hold or do not hold is carried out. This seeks, in part, to address the unresolved research issues. Chaos is shown to hold if all zeros of the noise transfer function lie outside the unit circle of radius two, provided the input is either periodic or persistently random (mod delta). When the filter satisfies a certain continuity condition, the conditions for chaos are extended, and more clear cut classifications emerge. Other specific chaos classifications are established. A study of the statistical properties of the error in dithered quantizers and sigma-delta modulators is pursued using the same state space model. A general treatment of the steady state error probability distribution is introduced, and results for predicting uniform steady state errors under various conditions are found. The uniformity results are applied to RPDF dithered systems to give conditions for a steady state error variance of delta squared over six. Numerical simulations support predictions of the analysis for the first-order case with constant input. An analysis of conditions on the model to obtain bounded internal stability or instability is conducted. The overall investigation of this thesis provides a theoretical approach upon which to orient future work, and initial steps of inquiry that can be advanced more extensively in the future.

<p>Sigma-delta modulators (SDM) have come up as an attractive candidatefor analog-to-digital conversion in single chip front ends thanks to the continuousimproving performance. The major disadvantage is the limited bandwidthdue to the need of oversampling. Therefore, extending these convertersto broadband applications requires lowering the oversampling ratio (OSR) inorder. The aim of this thesis is the investigation on the topology and structureof sigma-delta modulators suitable for wideband applications, e.g. wireline orwireless communication system applications having a digital baseband aboutone to ten MHz.It has recently become very popular to feedforward the input signal inwideband sigma-delta modulators, so that the integrators only process quantizationerrors. The advantage being that the actual signal is not distorted byopamp and integrator nonlinearities. An improved feedforward 2-2 cascadedstructure is presented based on unity-gain signal transfer function (STF). Theimproved signal-to-noise-ratio (SNR) is obtained by optimizing zero placementof the noise transfer function (NTF) and adopting multi-bit quantizer.The proposed structure has low distortion across the entire input range.In high order single loop continuous-time (CT) sigma-delta modulator, excessloop delay may cause instability. Previous techniques in compensation ofinternal quantizer and feedback DAC delay are studied especially for the feedforwardstructure. Two alternative low power feedforward continuous-timesigma-delta modulators with excess loop delay compensation are proposed.Simulation based CT modulator synthesis from discrete time topologies isadopted to obtain the loop filter coefficients. Design examples are given toillustrate the proposed structure and synthesis methodology.Continuous time quadrature bandpass sigma-delta modulators (QBSDM)efficiently realize asymmetric noise-shaping due to its complex filtering embeddedin the loops. The effect of different feedback waveforms inside themodulator on the NTF of quadrature sigma-delta modulators is presented.An observation is made that a complex NTF can be realized by implementingthe loop as a cascade of complex integrators with a SCR feedback digital-toanalogconverter (DAC), which is desirable for its lower sensitivity to loopmismatch. The QBSDM design for different bandpass center frequencies relativeto the sampling frequency is illustrated.The last part of the thesis is devoted to the design of a wideband reconfigurablesigma-delta pipelined modulator, which consists of a 2-1-1 cascadedmodulator and a pipelined analog-to-digital convertor (ADC) as a multi-bitquantizer in the last stage. It is scalable for different bandwidth/resolutionapplication. The detail design is presented from system to circuit level. Theprototype chip is fabricated in TSMC 0.25um process and measured on thetest bench. The measurement results show that a SNR over 60dB is obtainedwith a sampling frequency of 70 MHz and an OSR of ten.</p>

The main purpose of this thesis is to research High-Order Sigma-Delta Analog-to-Digital converter for precision measurement, a PI compensator and a third-order Sigma-Delta modulator has been proposed based on a second-order Sigma-Delta modulator. In accordance with the analysis result of frequency domain and time domain of system, we use third-order model because of better response with auxiliary software to simulate and implement the system, then measure modulator output variance for input variation. This converter circuit demonstrates that it can achieve the requirements of precision and linearity which the measure instrument demands.

The sigma-delta modulator is a popular signal amplitude quantization error (or noise) shaper used in oversampling analogue-to-digital and digital-to-analogue converter systems. The shaping of the noise frequency spectrum is performed by feeding back the quantization errors through a time delay element filter and feedback loop in the circuit, and by the addition of a possible stochastic dither signal at the quantizer. The aim in audio systems is to limit audible noise and distortions in the reconverted analogue signal. The formulation of the sigma-delta modulator as a discrete dynamical system provides a useful framework for the mathematical analysis of such a complex nonlinear system, as well as a unifying basis from which to consider other systems, from pseudorandom number generators to stochastic resonance processes, that yield equivalent formulations. The study of chaos and other complementary aspects of internal dynamical behaviour in previous research has left important issues unresolved. Advancement of this study is naturally facilitated by the dynamical systems approach. In this thesis, the general order feedback/feedforward sigma-delta modulator with multi-bit quantizer (no overload) and general input, is modelled and studied mathematically as a dynamical system. This study employs pertinent topological methods and relationships, which follow centrally from the symmetry of the circle map interpretation of the error state space dynamcis. The main approach taken is to reduce the nonlinear system into local or special case linear systems. Systems of sufficient structure are shown to often possess structured random, or random-like behaviour. An adaptation of Devaney's definition of chaos is applied to the model, and an extensive investigation of the conditions under which the associated chaos conditions hold or do not hold is carried out. This seeks, in part, to address the unresolved research issues. Chaos is shown to hold if all zeros of the noise transfer function lie outside the unit circle of radius two, provided the input is either periodic or persistently random (mod delta). When the filter satisfies a certain continuity condition, the conditions for chaos are extended, and more clear cut classifications emerge. Other specific chaos classifications are established. A study of the statistical properties of the error in dithered quantizers and sigma-delta modulators is pursued using the same state space model. A general treatment of the steady state error probability distribution is introduced, and results for predicting uniform steady state errors under various conditions are found. The uniformity results are applied to RPDF dithered systems to give conditions for a steady state error variance of delta squared over six. Numerical simulations support predictions of the analysis for the first-order case with constant input. An analysis of conditions on the model to obtain bounded internal stability or instability is conducted. The overall investigation of this thesis provides a theoretical approach upon which to orient future work, and initial steps of inquiry that can be advanced more extensively in the future.

The thesis proposes a third order continuous-time sigma delta modulator used in GSM. We used a special 1.5bit quantizer, and to use its three different states to reach a differential feedback path. That can improve the resolution of our circuit. Oversampling and noise shaping are two keys of sigma delta modulator. In structure, the continuous-time features can reduce power consumption. The proposed sigma delta modulator uses TSMC 0.35 m CMOS process and its sampling frequency is 10.8MHz, bandwidth is200KHz and oversampling ratio is 32.

Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switch’s speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulator’s power consumption is 302 mW from supply power of ± 1.65V.

In this thesis, a switched-current integrator with active amplifier feedback and dummy switch is proposed to increase the operation speed and reduce the non-ideal effects in traditional switched-current circuit. The active amplifier is designed in low gain and high bandwidth so that the oscillation can be avoided. We improve the operation speed and transmission error by the active amplifier feedback and reduce the CFT error by the dummy switch so that high resolution can be achieved. Then we apply the proposed integrator to the switched-current sigma-delta modulator. The sigma-delta modulator is simulated using TSMC 0.35£gm CMOS process with 3.3V power supply. We obtain 67dB PSNR, 66dB dynamic range(DR), and 40KHz bandwidth. The sampling frequency is 10.24MHz, the power supply is 3.3V and the power consumption is 19mW.

Digital-to-Analog Converters (DAC) form the feedback element in sigma-delta modulators. Any non-linearity in the DAC directly degrades the linearity of the modulator at low and medium frequencies. Hence, there is a need for designing highly linear DACs when used in high performance sigma-delta modulators. In this work, the impact of current mismatch on the linearity performance (IM3 and SQNR) of a 4-bit current steering DAC is analyzed. A selective calibration technique is proposed that is aimed at reducing the area occupancy of conventional linearization circuits. A statistical element selection algorithm for linearizing DACs is proposed. Current sources within the required accuracy are selected from a large set of current sources available. As compared with existing calibration techniques, this technique achieves higher accuracy and is more robust to variations in process and temperature. In contrast to existing data weighted averaging techniques, this technique does not degrade SNR performance of the ADC. A 5th order, 500 MS/s, 20 MHz sigma-delta modulator macro-model was used to test the linearity of the DAC.