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Low power architecture and circuit techniques for high boost wideband Gm-C filtersGambhir, Manisha 17 September 2007 (has links)
With the current trend towards integration and higher data rates, read channel
design needs to incorporate significant boost for a wider signal bandwidth. This
dissertation explores the analog design problems associated with design of such
'Equalizing Filter' (boost filter) for read channel applications.
Specifically, a 330MHz, 5th order Gm-C continuous time lowpass filter with
24dB boost is designed. Existing architectures are found to be unsuitable for low power,
wideband and high boost operation. The proposed solution realizes boosting zeros by
efficiently combining available transfer functions associated with all nodes of cascaded
biquad cells. Further, circuit techniques suitable for high frequency filter design are
elaborated such as: application of the Gilbert cell as a variable transconductor and a new
Common-Mode-Feedback (CMFB) error amplifier that improves common mode
accuracy without compromising on bandwidth or circuit complexity. A prototype is
fabricated in a standard 0.35mm CMOS process. Experimental results show -41dB of
IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation.
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Design and Simulation of All-CMOS Temperature-Compensated gm-C Bandpass Filters and Sinusoidal OscillatorsParajuli, Purushottam 16 August 2011 (has links)
No description available.
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NTSC Video Sync Separator and A Gm-C Anti-Aliasing Filter Design with Digitally Tunable Bandwidth for DVB-T ReceiversHung, Chien-Chih 24 June 2005 (has links)
The first topic of this thesis is a novel NTSC video sync separator (NSS) with a high-PSR (power supply rejection) bias generation circuitry (BGC) comprising a temperature compensation circuitry. The proposed BGC is composed of step-down regulators and a bandgap-based bias with cascode current control. The clamping voltages required for sync separation from an NTSC signal are generated.
The second topic is a temperature-compensated 6th order transconductance-C (Gm-C) anti-aliasing filter (AAF) with digitally tunable bandwidth which can be applied in the analog front-end circuit of DVB-T receivers. The proposed AAF is controlled by digital signals to provide three different baseband bandwidth (6, 7, 8 MHz) selection. A regulator with a bandgap circuitry supplies a stable voltage to suppress the variations of power and temperature. Moreover, a temperature -compensated circuitry is used to neutralize bandwidth drifting caused by the temperature variation. The bandwidth accuracy of the proposed design verified by HSPICE post-layout simulations is better than 3.28% at every PVT (process, supply voltage, temperature) corner. It is adequate for the DVB-T receivers¡¦ baseband processing.
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A Novel Q-Tuning Scheme for High-Q Continuous-Time Gm-C FiltersChen, Yung-Tai 18 July 2002 (has links)
A novel on chip automatic tuning circuit for Gm ¡V C continuous time filter is presented. The circuit is composed of an integrator, a frequency tuning circuit, and a Q tuning circuit. A 4th order Chebyshev low pass filter is also designed with the tuning circuitry. All circuits are designed by using the parameters of TSMC 0.25um process. The power supplies are ¡Ó2.5V, and the cutoff frequency is 10MHz. The main LPF exhibits passband ripple below 4dB, and stopband attenuation over 70dB. The equilibrium time for tuning circuits is less than 3£gseconds.
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Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applicationsLiu, Xuemei 12 April 2006 (has links)
Bandpass sigma-delta modulators combine oversampling and noise shaping to get
very high resolution in a limited bandwidth. They are widely used in applications that
require narrowband high-resolution conversion at high frequencies. In recent years interests
have been seen in wireless system and software radio using sigma-delta modulators to
digitize signals near the front end of radio receivers. Such applications necessitate clocking
the modulators at a high frequency (MHz or above). Therefore a loop filter is required in
continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime
circuits (e.g., using switched capacitors) where the maximum clocking rate is limited
by the bandwidth of Opamp, switchÂs speed and settling-time of the circuitry.
In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking
at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new
calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the
modulator. The continuous-time loop filter is based on Gm-C resonators. A novel
transconductance amplifier has been developed with high linearity at high frequency. Qfactor
of filter is enhanced by tunable negative impedance which cancels the finite output
impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal
standard analog CMOS technology. Postlayout simulation in CADENCE
demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1
MHz bandwidth. The modulatorÂs power consumption is 302 mW from supply power of ±
1.65V.
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Linearization and Efficiency Enhancement Techniques for RF and Baseband Analog CircuitsMobarak, Mohamed Salah Mohamed 2010 December 1900 (has links)
High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption.
An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth.
Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power.
High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.
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Low Power Filtering Techniques for Wideband and Wireless ApplicationsGambhir, Manisha 2009 August 1900 (has links)
This dissertation presents design and implementation of continuous time analog
filters for two specific applications: wideband analog systems such as disk drive channel
and low-power wireless applications. Specific focus has been techniques that reduce the
power requirements of the overall system either through improvement in architecture or
efficiency of the analog building blocks.
The first problem that this dissertation addresses is the implementation of
wideband filters with high equalization gain. An efficient architecture that realizes
equalization zeros by combining available transfer functions associated with a
biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with
24dB boost is designed using the proposed architecture. The prototype fabricated in
standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing
with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using
similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though
at the cost of much larger area.
Secondly, a complementary current mirror based building block is proposed,
which pushes the limits imposed by conventional transconductors on the powerefficiency
of Gm-C filters. Signal processing through complementary devices provides
good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly
7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC
technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in
1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter
realization occupies a relatively small area and is well suited for integration in deep
submicron technologies.
Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter
is designed for a ten bit continuous time sigma delta ADC architecture developed
specifically for fine-line CMOS technologies. Inverter based amplification and a
common mode feedback for such amplifiers are discussed. The filter consumes 5mW of
power and occupies an area of 0.07 mm2.
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Návrh elektronicky laditelných kmitočtových filtrů v technologii CMOS / Design of the electronically tunable frequency filters in CMOS technologyZlámal, Jiří January 2014 (has links)
This master thesis deals with the problematics of CT filters and focuses on Gm – C filter. Three linearisation techniques are listed and compared in terms of linear input range, distortion and retuning. In the practical part – second - order low – pass filter is designed and its tuning capabilities are examined.
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Návrh laditelného kmitočtového filtru 2. řádu v technologii CMOS / Design of tunable second order frequency filter in CMOS technologyHrdina, Robin January 2016 (has links)
This master’s thesis deals with the design of tuneable frequency second order filter in CMOS technology. The thesis describes the design of a transconductor and its utilization for tunable gm-C filter. The design and all simulations were made in Cadence Spectre and Virtuoso software. Limitedly Orcad Pspice and SNAP were also used.
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On the Design of an Analog Front-End for an X-Ray DetectorAmin, Farooq ul January 2009 (has links)
<p>Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.</p><p>A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.</p><p>The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.</p>
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