Research was performed to optimize the high-efficiency jet ejector geometry by varying motive velocities from Mach 0.50 to 3.25, and mass flow ratio from 0.02 to 100.0. The high-efficiency jet ejector was simulated by Fluent Computational Fluid Dynamics (CFD) software. A conventional finite-volume scheme was utilized to solve two-dimensional transport equations with the standard k-ε turbulence model. In the optimization study of the constant-area jet ejectors, all parameters were expressed in dimensionless terms. The objective of the study was to investigate the optimal length, throat diameter, and optimal nozzle diameter at any operating conditions. Also, the optimum compression ratio and efficiency were calculated. By comparing simulation results to an experiment, CFD modeling has shown high-quality results. The overall deviation was 8.19%, thus confirming the reliability of the modeling results. The results from the optimization study indicate that the jet ejector efficiency improves significantly compared to a conventional jet-ejector design. In cases with a subsonic motive velocity, the efficiency of the jet ejector is greater than 90%. A high compression ratio can be achieved with greater motive velocity and mass flow ratio. The ejector performance between the optimal jet ejectors and conventional jet ejectors provided by Graham Corporation was compared. The results show that substituting a single optimal jet ejector for a single conventional ejector reduces the motive stream consumption by about 10% to 30%, which could decrease operating costs tremendously. Dimensionless group analysis reveals that the research results are valid for any fluid, operating pressure and geometric scale for a given motive-stream Mach number and momentum ratio. The explanation of how to implement the optimization results and selecting the best operating conditions to minimize the motive stream consumption was included at the end of the dissertation.

Dans cette étude, nous utilisons des caractéristiques locales/globales en vue d’améliorer la chaîne de transmission des séquences de vidéos. Ce travail est divisé en quatre parties principales qui mettent à profit les caractéristiques de contenu vidéo. La première partie introduit un modèle de prédiction de paramètres d’un encodeur basé sur la complexité du contenu. Ce modèle utilise le débit, la distorsion, ainsi que la complexité de différentes configurations de paramètres afin d’obtenir des valeurs souhaitables (recommandées) de paramètres d’encodage. Nous identifions ensuite le lien en les caractéristiques du contenu et ces valeurs recommandées afin de construire le modèle de prédiction. La deuxième partie illustre le schéma de l’encodage à description multiple (Multiple Description Coding ou MDC, en anglais) que nous proposons dans ces travaux. Celui-ci est optimisé pour des MDC d’ordre-hauts. Le décodage correspondant et la procédure de récupération de l’erreur contenu-dépendant sont également étudiés et identifiés. La qualité de la vidéo reçue a été évaluée subjectivement. En analysant les résultats des expériences subjectives, nous introduisons alors un schéma adaptatif, c’est-à-dire adapté à la connaissance du contenu vidéo. Enfin, nous avons simulé un scénario d’application afin d’évaluer un taux de débit réaliste. Dans la troisième partie, nous utilisons une carte de déplacement, calculées au travers des propriétés de mouvement du contenu vidéo, comme entrée pour l’algorithme de masquage d’erreur par recouvrement (inpainting based error concealment algorithm). Une expérience subjective a été conduite afin d’évaluer l’algorithme et d’étudier la perturbation de l’observateur au visionnage de la vidéo traitée. La quatrième partie possèdent deux sous-parties. La première se penche sur les algorithmes de sélections par HRC pour les grandes bases de données de vidéos. La deuxième partie introduit l’évaluation de la qualité vidéo utilisant la connaissance du contenu global non-référencé. / In this work, the global/local content characteristics are utilized in order to improve the delivery chain of the video sequences. The work is divided into four main parts that take advantages of video content features. The first part introduces a joint content-complexity encoder parameters prediction model. This model uses bitrate, distortion, and complexity of different parameters configurations in order to get the recommended encoder parameters value. Then, the links between content features and the recommended values are identified. Finally, the prediction model is built using these features and the recommended encoder parameter values. The second part illustrates the proposed multiple description coding (MDC) scheme that is optimized for high-order MDC. The corresponding decoding and content-dependent error recovery procedures are also identified. The quality of the received videos is evaluated subjectively. By analyzing the subjective experiment results, an adaptive, i.e. content-aware, scheme is introduced. Finally, an application scenario is simulated to study the realistic bitrate consumption. The third part uses the motion properties of a content to introduce a motion map that will be used as an input for the modified state-of-the-art inpainting based error concealment algorithm. A subjective experiment was conducted to evaluate the algorithm and also to study the content-aware observer’s disturbance when perceiving the processed videos. The fourth part has two sub-parts, the first one is about HRC selection algorithms for the large-scale video database with an improved performance evaluation measures for video quality assessment algorithms using training and validation sets. The second part introduces global content aware no-reference video quality assessment.

Argon replacing nitrogen has been examined as a new engine cycle to reach high efficiency. Experiments were carried out under Homogeneous Charge Compression Ignition (HCCI) conditions using a single cylinder variable compression ratio Cooperative Fuel Research (CFR) engine. Isooctane has been used as the fuel for this study. All the parameters were kept fixed but the compression ratio to make the combustion phasing constant. Typical engine outputs and emissions were compared to conventional cycles with both air and synthetic air. It has been found that the compression ratio of the engine must be significantly reduced while using argon due to its higher specific heat ratio. The resulting in-cylinder pressure was lower but combustion remains aggressive. However, greater in-cylinder temperatures were reached. To an end, argon allows gains in fuel efficiency, in unburned hydrocarbon and carbon monoxide, as well as in indicated efficiency. A higher nitrogen oxide concentration while replacing nitrogen by argon was observed but the origin remains to be identified. The concept should therefore be able to reach zero-NOx emissions as no nitrogen should be present.

Organic Light Emitting Diodes (OLEDs) are widely viewed as next generation platform for flat panel displays and solid state lighting. Currently, OLED efficiency is not high due to high driving voltage. Molybdenum trioxide (MoO3) is ideal for p-type doping of the wide bandgap organic semiconductor 4,4’-bis-9-carbozyl biphenyl (CBP). With p-type doped CBP layer as Hole Transport Layer (HTL), driving voltage can be significantly reduced. Effective design for doped OLED structure consists of a HTL with doped layer from 20nm to 40nm and MoO3 concentration above 5%, the optimized OLED with doped CBP HTL present an 18% improvement over a standard device with CBP HTL at 100mA/cm2. Injection is found to be the principle cause of the reduction of driving voltage and shows close relations to doped layer thickness. Also charge balance is an important factor for high current efficiency, doped layer can be used as tools to promote charge balance.

Organic Light Emitting Diodes (OLEDs) are widely viewed as next generation platform for flat panel displays and solid state lighting. Currently, OLED efficiency is not high due to high driving voltage. Molybdenum trioxide (MoO3) is ideal for p-type doping of the wide bandgap organic semiconductor 4,4’-bis-9-carbozyl biphenyl (CBP). With p-type doped CBP layer as Hole Transport Layer (HTL), driving voltage can be significantly reduced. Effective design for doped OLED structure consists of a HTL with doped layer from 20nm to 40nm and MoO3 concentration above 5%, the optimized OLED with doped CBP HTL present an 18% improvement over a standard device with CBP HTL at 100mA/cm2. Injection is found to be the principle cause of the reduction of driving voltage and shows close relations to doped layer thickness. Also charge balance is an important factor for high current efficiency, doped layer can be used as tools to promote charge balance.

High efficiency air blowers to meet future portable aerosol sampling applications were designed, fabricated, and evaluated. A Centrifugal blower was designed to achieve a flow rate of 100 L/min (1.67 x 10^-3 m^3/s) and a pressure rise of WC " 4 (1000 PA). Commercial computational fluid dynamics (CFD) software, FLUENT 6.1.22, was used extensively throughout the entire design cycle. The machine, Reynolds number (Re) , was around 10^5 suggesting a turbulent flow field. Renormalization Group (RNG) κ−ε turbulent model was used for FLUENT simulations. An existing design was scaled down to meet the design needs. Characteristic curves showing static pressure rise as a function of flow rate through the impeller were generated using FLUENT and these were validated through experiments. Experimentally measured efficiency (ηEXP) for the base-design was around 10%. This was attributed to the low efficiency of the D.C. motor used. CFD simulations, using the κ−ε turbulent model and standard wall function approach, over-predicted the pressure rise values and the percentage error was large. Enhanced wall function under-predicted the pressure rise but gave better agreement (less than 6% error) with experimental results. CFD predicted a blower scaled 70% in planar direction (XZ) and 28% in axial direction (Y) and running at 19200 rpm (70xz_28y@19.2k) as the most appropriate choice. The pressure rise is 1021 Pa at the design flow rate of 100 L/min. FLUENT predicts an efficiency value based on static head (ηFLU) as 53.3%. Efficiency value based on measured static pressure rise value and the electrical energy input to the motor (ηEXP) is 27.4%. This is almost a 2X improvement over the value that one gets with the hand held vacuum system blower.

Current improvements in gas turbine engine performance have arisen primarily due to increases in turbine inlet temperature and compressor pressure ratios. However, a maximum possible turbine inlet temperature exits in the form of the adiabatic combustion temperature of the fuel. In addition, thermal limits of turbine blade materials also places an upper bound on turbine inlet temperatures. Thus, the current strategy for improving gas turbine efficiency is inherently limited. Introduction of a new gas turbine, based on an alternative work cycle utilizing isothermal combustion (i.e. combustion within the turbine) affords significant opportunities for improving engine output and/or efficiency. However, implementation of such a scheme presents a number of technological challenges such as holding a flame in high-speed flow. The current research is aimed at determining whether such a combustion scheme is feasible using computational methods. The geometry, a simple 2-D cascade utilizes surface injection within the stator or rotor boundary layers (including the rotor pressure side recirculation zone (a natural flame holder). Computational methods utilized both steady and time accurate calculations with transitional flow as well as laminar and turbulent combustion and species transport. It has been determined that burning within a turbine is possible given a variety of injection schemes using "typical" foil geometries under "typical" operating conditions. Specifically, results indicate that combustion is self-igniting and, hence, self-sustaining given the high temperatures and pressures within a high pressure turbine passage. Deterioration of aerodynamic performance is not pronounced regardless of injection scheme. However, increased thermal loading in the form of higher adiabatic surface temperatures or heat transfer is significant given the injection and burning of the fuel within the boundary layer. This increase in thermal loading is, however, minimized when injection takes place in or near a recirculation zone. The effect of injection location on pattern factors indicates that suction side injection minimizes temperature variation downstream of the injection surface (for rotor injection only). In addition, the most uniform temperature profile (in the flow direction) is achieved by injection fuel and combustion nearest to the source of work extraction. Namely, injection at the rotor produces the most "isothermal" temperature distribution. Finally, a pseudo direct simulation of an isothermal machine is conducted by combining simulation data and assumed processes. The results indicate that isothermal combustion results in an increase in turbine specific work and efficiency over the equivalent Brayton cycle. / Master of Science

Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. At first, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. For laptop application, the VR input voltage range covers the battery voltage range and the adaptor voltage. In the meantime, microprocessors will run at very low voltage (sub 1V), and will consume up to 150A of current, and will have dynamics of about 400A/us. The current VR solution is the 12V-input multiphase interleaved buck converter. The switching frequency is around 300KHz. This approach has several limitations for the future. OSCON capacitor is one limitation due to its large ESR and ESL; the low switching frequency the second limitation and the large inductance is the third limitation. Analysis shows that the all-ceramic solution is a better solution than the OSCON solution when the VR switching frequency reaches 1MHz. However, the 12V-input multiphase buck converter suffers low efficiency at high switching frequency, which rules out a legitimate chance of the current VR topology benefiting from high switching frequency. The extreme duty cycle is the fundamental reason why the 12V-input multiphase buck converter is not suitable for future VRs. Employing the transformer concept can extend duty cycle, and therefore offer an opportunity to improve efficiency. The push-pull buck (PPB) converter is proposed as a solution. The efficiency is improved compared with the buck converter. Integrated magnetic techniques can be used to further improve the efficiency and simplify the implementation. The impact of transformer concept on transient response is analyzed. The PPB converter efficiency is still not satisfactory at 1MHz due to the switching loss. Switching loss being a barrier, soft switching is needed. The proposed soft-switched phase-shift buck (PSB) converter achieves soft switching for the top switches. Highly efficient power conversion is achieved at high switching frequency. The integrated magnetics makes the implementation concise and delivers good performance. Given that the PSB converter has good performance, the matrix-transformer phase-shift buck (MTPSB) converter is a simplified version of the four-phase PSB converter. The MTPSB converter trades off some performance with circuit complexity. This feature establishes itself as a very cost-effective solution for future VRs. The magnetic structure of the MTPSB converter is also very simple with the use of integrated magnetics. Mobile CPUs are used in laptop computers. They require very challenging power management. The challenges for a laptop VR are different from and greater than those for a desktop VR. A laptop VR needs to have high efficiency at both heavy load and light load, good transient response and small and light form-factor, and work well with the wide input voltage range. Future mobile CPUs demand very aggressive power. The current single-stage VR approach cannot provide a suitable solution for the future. The PSB converter has disadvantages in light-load efficiency and does not work well with wide input voltage range; therefore it is not a suitable solution for laptop VRs although it is still a suitable solution for desktop VRs. The two-stage approach solves the wide-input-voltage-range issue and improves efficiency at heavy load significantly. The intermediate bus voltage Vbus is a very important parameter impacting overall efficiency. There is not one optimal Vbus value for all load conditions. The heavier the load, the higher the optimal Vbus. Based on this fact, the ABVP control is proposed. Vbus is adaptively positioned according to the load current therefore optimal Vbus is achieved under most conditions. Experimental results verify the theoretical prediction. The ONP control is another control scheme proposed to improve the light-load efficiency. By selecting optimal number of phases based on mobile processor power states, the VR light-load efficiency is improved. Experimental results show the proof. The baby-buck concept is the third concept proposed to improve the very-light-load efficiency. By operating the baby-buck channel, the two-stage VR improves efficiency at very light load. The two-stage VR featuring the three proposed control schemes has much higher efficiency than the single-stage VR over a very wide load range; therefore the battery life is extended. The two-stage VR with the proposed control schemes is a good solution for future laptop VRs. The problem solving process in this work proves that good solutions in isolated converters can be modified to fit into the non-isolated application. Non-isolated converters and isolated converters are not two separated worlds. On the contrary, these two worlds have many things in common. Good concepts can be transplanted from one world to another with minor modification and many problems can be solved this way. Another proven point in this work is that sometimes the solution is a fundamental, such as the change of power delivery architecture. One should not be limited by what is available right now, and should think outside the box. Once a fundamental change is made, it is very beneficial to take full advantage of the change, as it provides new opportunities. / Ph. D.

It is perceived that Moore's Law will prevail at least for the next decade, with continuous advancements of processing technologies for very-large-scale integrated (VLSI) circuits. Nano technology is driving VLSI circuits in a path of greater transistor integration, faster clock frequency, and lower operation voltage. This has imposed a new challenge for delivering high- quality power to modern processors. Power management technology is critical for transferring the required high current in a highly efficient way, and accurately regulating the sub-1V voltage in very fast dynamic transient response conditions. Furthermore, the VRs are limited in a given area and the power density is important to save the precious real estate of the motherboard. Based on the power delivery path model, the analysis results show that as long as the bandwidth can reach around 350 kHz, the bulk capacitor of the VR can be completely eliminated, which means significant savings in cost and real estate. Analysis also indicates that 650kHz bandwidth can reduce the number of the decoupling capacitor from 230 to 50 for future microprocessor case. Beyond 650kHz, the reduction is not obvious any more due to the parasitic components along the power delivery path. Following the vision of high bandwidth, the VRs need to operate at much higher frequency than today's practice. Unfortunately, the multiphase buck converter cannot benefit from it due to the low efficiency at high switching frequency. The extreme duty is the bottleneck. The extreme duty cycle increases VR switching loss, reverse recovery loss, and conduction loss; therefore makes the 12V-input VR efficiency drop a good deal when compared with 5V-input VR efficiency. Two-stage approach is proposed in this dissertation to solve this issue. The analysis shows that the two-stage conversion has much better high frequency capability than the conventional single stage VRs. Based on today's commercial devices, 2-MHz is realized by the hardware and 350kHz bandwidth is achieved to eliminate the output bulk capacitors. Further improvement based on future devices and several proposed methods of reducing switching loss and body diode loss can push the switching frequency up to 4MHz while maintaining good efficiency. Such a high frequency makes the high bandwidth design (650kHz) feasible. Hence, the output capacitance can be significantly reduced to save cost and real estate. The two-stage concept is also effective in laptop computer and 48V DPS applications. It has been experimentally proved that two-stage VR is able to achieve higher switching frequency than single stage not only at full load condition but also at light load condition by the proposed ABVP and AFP concept based on two-stage configuration. These unique control strategies make the two-stage approach even more attractive. As the two-stage approach is applied to 48V DPS applications, such as telecommunication system and server systems, more efficient and higher power density power supply can be achieved while greatly cut down the cost. Therefore, after the two-stage approach is proposed, it has been widely adopted by the industry. In order to further reduce the output capacitance, the power architecture of computer needs to be modified. Based on two-stage approach, one possible solution is to move the second stage VR up to the OLGA board. Based on this structure, the parasitics can be dramatically reduced and the number of the cavity capacitor is reduced from 50 to 14. By reducing ESL of the capacitor, the output capacitance could be further reduced. After that and based on two-stage approach again, VR+LR structure is discussed, which provides the opportunity to reduce the output capacitance and integrate the power supply with CPU. The feasibility is studied in this dissertation from both power loss reduction and output capacitance reduction perspectives. Experimental results prove that LR can significantly reduce the voltage spike while minimizing the output capacitance. As a conclusion, the two-stage approach is a promising solution for powering future processors. It is widely effective in computer and communication systems. Far beyond that, it provides a feasible platform for new architectures to power the future microprocessors. / Ph. D.

In order to meet demands for faster and more efficient data processing, modern microprocessors are being designed with lower voltage implementations. The processor voltage supply in future generation processors will decrease to 1.1 V ~ 1.8V. More devices will be packed on a single processor chip, and processors will operate at higher frequencies, beyond 1GHz. Therefore, microprocessors need aggressive power management. Future generation processors will draw current up to 50 A ~ 100 A [2]. These demands, in turn, will require special power supplies and Voltage Regulator Modules (VRMs) to provide lower voltages with higher currents and fast transient capabilities for microprocessors. This work presents several low-voltage high-current VRM technologies for future generation data processing, communication, and portable applications. The developed advanced VRMs with these new technologies have advantages over conventional ones in power density, efficiency, transient response, reliability, and cost. The multi-module interleaved quasi-square-wave VRM topology achieves a very fast transient response and a very high power density. This topology significantly reduces the filter inductance and capacitance, while having small output and input ripples. The analysis, design, and experimental verification for this new topology are presented in this work. The current sensing and current sharing techniques are developed with simple and cost-effective implementations. With this technique, traditional current transformers and sensing resistors are not required, and the inductance value, MOSFET on resistance and other parasitics have no effect on current sharing results. The design principles are developed and experimentally verified. A generalized approach and an extension of the novel current sharing control are presented in this work. The techniques for improving VRM light load efficiency are developed in this work. By utilizing the duty cycle signal, VRMs can be implemented with advanced power management functions to reduce further the power consumption at light loads to extend the battery-operation time in portable systems or to facilitate the compliance with various "energy star" ("green" power) requirements in office systems. Four improved approaches are presented and verified with experimental results. The high-input-voltage VRM topology, push-pull forward converter, can be used in high-bus-voltage distributed power systems. This converter has a high efficiency, a high power density, a fast transient response, and can be easily packaged as a standard module. The circuit design and experimental evaluation are addressed to demonstrate the operation principles and advantages of this topology. / Ph. D.