Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

Integrated high-Q continuous-time filters require adaptive tuning circuits that will correct the filter parameters such as center frequency and quality factor (Q). Three different automatic tuning techniques are introduced. In all of the proposed methods, frequencyand quality factor tuning loops are controlled digitally, providing stable tuning by activating only one loop at a given time. In addition, a direct relationship between passband gain and quality factor is not required, so the techniques can be applied to active LC filters as well as Gm-C filters. The digital-tuning method based on phase comparison was verified with 1% tuning accuracy at 5.5 MHz for Q of 20. It uses phase information for both Q and center-frequency tuning. The filter output phase is tuned to the known references, which are generated by a frequency synthesizer. The core tuning circuit consists of D flip-flops (DFF) and simple logic gates. DFFs are utilized to perform binary phase comparisons. The second method, high-order digital tuning based on phase comparison, is an extension of the previous technique to high-order analog filters without depending on the master-slave approach. Direct tuning of the overall filter response is achieved without separating individual biquad sections, eliminating switches and their parasitics. The tuning system was verified with a prototype 6th order bandpass filter at 19 MHz with 0.6 MHz bandwidth, which was fabricated in a conventional 0.5 [mu]m CMOS technology. Analysis of different practical limitations is also provided. Finally, the digital-tuning method based on magnitude comparison is proposed for second-order filters for higher frequency operations. It incorporates a frequency synthesizer to generate reference signals, an envelope detector and a switched comparator to compare output magnitudes at three reference frequencies. The theoretical analysis of the technique and the simulation results are provided.

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.

This dissertation presents design and implementation of continuous time analog filters for two specific applications: wideband analog systems such as disk drive channel and low-power wireless applications. Specific focus has been techniques that reduce the power requirements of the overall system either through improvement in architecture or efficiency of the analog building blocks. The first problem that this dissertation addresses is the implementation of wideband filters with high equalization gain. An efficient architecture that realizes equalization zeros by combining available transfer functions associated with a biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with 24dB boost is designed using the proposed architecture. The prototype fabricated in standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though at the cost of much larger area. Secondly, a complementary current mirror based building block is proposed, which pushes the limits imposed by conventional transconductors on the powerefficiency of Gm-C filters. Signal processing through complementary devices provides good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly 7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in 1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter realization occupies a relatively small area and is well suited for integration in deep submicron technologies. Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter is designed for a ten bit continuous time sigma delta ADC architecture developed specifically for fine-line CMOS technologies. Inverter based amplification and a common mode feedback for such amplifiers are discussed. The filter consumes 5mW of power and occupies an area of 0.07 mm2.

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.

Operational transconductance amplifier and capacitor (OTA-C) filters have outstood among different types of filter due to high frequency and low power capabilities in the main stream digital CMOS technology. They have been widely used in computer hard disk drive (HDD) and wireless communication transceivers. OTA-C filters based on cascade and passive ladder simulation are well-known. However, multiple loop feedback (MLF) OTA-C filters which have certain advantages still have the scope for further research. So far there have been no explicit formulas for current-mode leapfrog (LF) filter design and performance evaluation of current-mode MLF OTA-C filters are still lacking. From application viewpoints, read channels for computer hard disk drives require very high frequency continuous-time filters. This automatically disqualifies active- RC/MOSFET-C filters and OTA-C filters become the only solution. In wireless communications, active-RC/MOSFET-C filters have been proved useful for mobile systems whose baseband frequency falls below a few MHz. However, for wireless LANs with the frequency of several tens of MHz, OTA-C filters are a strong candidate. Whilst in HDD read channels, cascaded OTA-C architectures have been most utilized and in wireless receivers, OTA-C structures based on ladder simulation have been popular, MLF OTA-C filters have not been practically used in either of the applications. This thesis describes some novel designs and applications of multiple loop feedback OTA-C filters with extensive CMOS simulations. Analogue filters for computer hard disk drive systems are first reviewed; the state of the art and design considerations are provided. Three VHF linear phase lowpass OTA-C filters are then designed, which include a seventh-order and a fifth-order current-mode filter based on the follow-the-leader-feedback (FLF) structure and a seventh-order voltage-mode filter using the inverse FLF (IFLF) configuration. These filters all have very low power consumption. The synthesis and design of general current-mode LF OTA-C filters are conducted next. Iterative design formulas for both all-pole and finite-zero functions are derived and explicit formulas for up to sixth-orders are given. These formulas are very easy to use for designing any type of characteristics. Subsequently, linear phase lowpass OTA-C filter design for HDD read channels using LF structures are investigated in details. A current-mode filter and a voltage-mode filter using the fifth-order LF structure are presented. The two filters can operate up to 800MHz and have very small passband phase ripple. Analogue filters for wireless communication baseband applications are also reviewed thoroughly in this thesis, where the design of a fourth-order current-mode FLF Butterworth lowpass OTA-C filter for multi-standard receivers is presented. Then two fifth-order current-mode elliptic lowpass OTA-C filters based on respective LF and FLF structures for wireless communication baseband are designed. Fifth-order voltage-mode IFLF and LF elliptic lowpass filters are also presented. All these MLF baseband filters designed can operate up to 40MHz to cover all important wireless and mobile standards. Simulations show that the LF structures have better dynamic range and stopband attenuation performances than the FLF and IFLF configurations.

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications.